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公开(公告)号：US20230055695A1
公开(公告)日：2023-02-23
申请号：US18045128
申请日：2022-10-07
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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公开(公告)号：US11281495B2
公开(公告)日：2022-03-22
申请号：US16113211
申请日：2018-08-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Rex Eldon McCrary
Abstract: A system and method for providing security of sensitive information within chips using SIMD micro-architecture are described. A command processor within a parallel data processing unit, such as a graphics processing unit (GPU), schedules commands across multiple compute units based on state information. When the command processor determines a rescheduling condition is satisfied, it causes the overwriting of at least a portion of data stored in each of the one or more local memories used by the multiple compute units. The command processor also stores in the secure memory a copy of state information associated with a given group of commands and later checks it to ensure corruption by a malicious or careless program is prevented.
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公开(公告)号：US20210011760A1
公开(公告)日：2021-01-14
申请号：US16938381
申请日：2020-07-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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公开(公告)号：US20180239635A1
公开(公告)日：2018-08-23
申请号：US15438466
申请日：2017-02-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Michael J. Mantor , Randy Wayne Ramsey , Rex Eldon McCrary , Harry J. Wise
IPC: G06F9/48
Abstract: Systems, apparatuses, and methods for suspending and restoring operations on a processor are disclosed. In one embodiment, a processor includes at least a control unit, multiple execution units, and multiple work creation units. In response to detecting a request to suspend a software application executing on the processor, the control unit sends requests to the plurality of work creation units to stop creating new work. The control unit waits until receiving acknowledgements from the work creation units prior to initiating a suspend operation. Once all work creation units have acknowledged that they have stopped creating new work, the control unit initiates the suspend operation. Also, when a restore operation is initiated, the control unit prevents any work creation units from launching new work-items until all previously in-flight work-items have been restored to the same work creation units and execution units to which they were previously allocated.
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公开(公告)号：US20180210657A1
公开(公告)日：2018-07-26
申请号：US15417011
申请日：2017-01-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Rex Eldon McCrary , Michael J. Mantor , Alexander Fuad Ashkar , Harry J. Wise
CPC classification number: G06F3/0607 , G06F3/0619 , G06F3/0634 , G06F3/065 , G06F3/067 , G06F9/4881 , G06F9/50
Abstract: Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.
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Patent Agency Ranking
公开(公告)号：US20180082398A1
公开(公告)日：2018-03-22
申请号：US15270679
申请日：2016-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Harry J. Wise , Rex Eldon McCrary , Angel E. Socarras
CPC classification number: G06T1/20 , G06F1/325 , G06F3/0604 , G06F3/0638 , G06F3/0685 , G06T1/60
Abstract: An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. The packets are filtered based on a comparison of hardware state information included in the packet and hardware state information stored in the adaptive list. The adaptive list is modified in response to filtering the first packet. The filters can include a hardware filter and a software filter that selectively filters the packets based on whether the graphics processing core is limiting throughput. The adaptive list can be implemented as content-addressable memory (CAM), a cache, or a linked list.
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公开(公告)号：US11934873B2
公开(公告)日：2024-03-19
申请号：US17946213
申请日：2022-09-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Rex Eldon McCrary
IPC: G06F9/54 , G06F9/30 , G06F9/38 , G06F9/48 , G06F12/0831
CPC classification number: G06F9/4893 , G06F9/30079 , G06F9/3867 , G06F9/542 , G06F9/544 , G06F12/0835
Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.
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公开(公告)号：US11467870B2
公开(公告)日：2022-10-11
申请号：US16938381
申请日：2020-07-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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公开(公告)号：US10955901B2
公开(公告)日：2021-03-23
申请号：US15721109
申请日：2017-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Fuad Ashkar , Angel E. Socarras , Rex Eldon McCrary
IPC: G06F1/00 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F1/3287 , G06F1/3203
Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).
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公开(公告)号：US10725822B2
公开(公告)日：2020-07-28
申请号：US16050948
申请日：2018-07-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
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