公开(公告)号：US20230393194A1

公开(公告)日：2023-12-07

申请号：US18236930

申请日：2023-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao WANG ,  Tsung-Tang TSAI ,  Chih-Yi HUANG

IPC: G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L23/00

CPC classification number: G01R31/2896 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/552 ,  H01L25/18 ,  H01L24/16 ,  H01L21/563

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

公开(公告)号：US20220139824A1

公开(公告)日：2022-05-05

申请号：US17090671

申请日：2020-11-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Yi HUANG ,  Chen-Chao WANG ,  Mi-Chun HUNG

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.

公开(公告)号：US20200335858A1

公开(公告)日：2020-10-22

申请号：US16388828

申请日：2019-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Sheng-Chi HSIEH ,  Chen-Chao WANG ,  Teck-Chong LEE

IPC: H01Q1/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/13 ,  H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01Q23/00

Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.

公开(公告)号：US20240186193A1

公开(公告)日：2024-06-06

申请号：US18439743

申请日：2024-02-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao WANG ,  Chih-Yi HUANG ,  Keng-Tuan CHANG

IPC: H01L21/66 ,  H01L23/485 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L22/22 ,  H01L23/485 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US20230215810A1

公开(公告)日：2023-07-06

申请号：US17566579

申请日：2021-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Chen-Chao WANG ,  Chang Chi LEE

IPC: H01L23/552 ,  H01L23/31 ,  H01L49/02 ,  H01L25/16

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L28/10 ,  H01L28/40 ,  H01L25/16

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

公开(公告)号：US20210202353A1

公开(公告)日：2021-07-01

申请号：US16732054

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ming-Fong JHONG ,  Chen-Chao WANG ,  Hung-Chun KUO

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.

公开(公告)号：US20210175175A1

公开(公告)日：2021-06-10

申请号：US16706533

申请日：2019-12-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Fu-Chen CHU ,  Hung-Chun KUO ,  Chen-Chao WANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.

公开(公告)号：US20230253302A1

公开(公告)日：2023-08-10

申请号：US17669231

申请日：2022-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Chen-Chao WANG ,  Chang Chi LEE

IPC: H01L23/498 ,  H01L25/16

CPC classification number: H01L23/49838 ,  H01L25/16

Abstract: An electronic package is disclosed. The electronic package includes an electronic component and a plurality of power regulating components. The plurality of power regulating components includes a first power regulating component and a second power regulating component. A first power path is established from the first power regulating component to a backside surface of the electronic component. A second power path is established from the second power regulating component to the backside surface of the electronic component.

公开(公告)号：US20220115276A1

公开(公告)日：2022-04-14

申请号：US17067565

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao WANG ,  Chih-Yi HUANG ,  Keng-Tuan CHANG

IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/485

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US20210104461A1

公开(公告)日：2021-04-08

申请号：US16593884

申请日：2019-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-I WU ,  Chen-Chao WANG

IPC: H01L23/528

Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.