Abstract:
Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
Abstract:
Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
Abstract:
Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.
Abstract:
Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
Abstract:
Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
Abstract:
A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
Abstract:
Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
Abstract:
A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).
Abstract:
Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.