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公开(公告)号：US11914983B2
公开(公告)日：2024-02-27
申请号：US17898013
申请日：2022-08-29
Applicant: Apple Inc.
Inventor： Christian T. Martelock , Ali Sazegari , Eric Bainville
CPC classification number: G06F8/63 , G06F8/658 , G06F9/44505
Abstract: Aspects and features include using a virtual disk image to improve computational performance when applying a software patch. Compressed extents within a stored disk image are detected. The compressed extents are virtually reordered to form compressed forks within a virtual disk image and the compressed forks are selected for decompression based on code to be patched. A decompressed fork with the patch is virtually written to the same or another virtual disk image as an updated fork, and the virtual disk image is used to write to storage, either to overwrite the same stored disk image or to produce an updated, compressed disk image. In some examples, the virtual disk image is validated prior to writing to the compressed image by comparing an output hash from the compressed disk image with a known hash to validate the virtual disk image.
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公开(公告)号：US11748098B2
公开(公告)日：2023-09-05
申请号：US17308738
申请日：2021-05-05
Applicant: Apple Inc.
Inventor： Ali Sazegari , Chris Cheng-Chieh Lee
CPC classification number: G06F9/30036 , G06F11/1004
Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion written to the result vector operand.
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公开(公告)号：US20220357947A1
公开(公告)日：2022-11-10
申请号：US17308738
申请日：2021-05-05
Applicant: Apple Inc.
Inventor： Ali Sazegari , Chris Cheng-Chieh Lee
Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion written to the result vector operand.
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公开(公告)号：US11461275B2
公开(公告)日：2022-10-04
申请号：US16692840
申请日：2019-11-22
Applicant: Apple Inc.
Inventor： Lars M. Lindberg , Ali Sazegari
Abstract: Methods for lossy and lossless pre-processing of image data. In one embodiment, a method for lossy pre-processing image data, where the method may include, at a computing device: receiving the image data, where the image data includes a model having a mesh, the mesh includes vertices defining a surface, the vertices including attribute vectors, and the attribute vectors including values. The method also including quantizing the values of the attribute vectors to produce modified values, where a precision of the modified values is determined based on a largest power determined using a largest exponent of the values, encoding pairs of the modified values into two corresponding units of information. The method also including, for each pair of the pairs of the modified values, serially storing the two corresponding units of information as a data stream into a buffer, and compressing the data stream in the buffer.
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公开(公告)号：US11341210B2
公开(公告)日：2022-05-24
申请号：US16425868
申请日：2019-05-29
Applicant: Apple Inc.
Inventor： Asaf Hargil , Ali Sazegari
Abstract: This application relates to a multi-layer convolution operation. The multi-layer convolution operation is optimized for a vector processing unit having a number of data paths configured to operate on vector operands containing a number of elements processed in parallel by the data paths. The convolution operation specifies a convolution kernel utilized to filter a multi-channel input and generate a multi-channel output of the convolution operation. A number of threads are generated to process blocks of the multi-channel output, each block comprising a set of windows of a number of channels of the multi-channel output. Each window is a portion of the array of elements in a single layer of the multi-channel output. Each thread processes a block in accordance with an arbitrary width of the block, processing a set of instructions for each sub-block of the block having a well-defined width, the instructions optimized for the vector processing unit.
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Patent Agency Ranking
公开(公告)号：US20200241876A1
公开(公告)日：2020-07-30
申请号：US16847068
申请日：2020-04-13
Applicant: Apple Inc.
Inventor： O-Cheng Chang , Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a processor (e.g. a CPU) may offload transcendental computation to a computation engine that may efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.
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公开(公告)号：US20200034145A1
公开(公告)日：2020-01-30
申请号：US16043772
申请日：2018-07-24
Applicant: Apple Inc.
Inventor： Eric Bainville , Jeffry E. Gonion , Ali Sazegari , Gerard R. Williams, III
Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.
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公开(公告)号：US20190250917A1
公开(公告)日：2019-08-15
申请号：US15896582
申请日：2018-02-14
Applicant: Apple Inc.
Inventor： O-Cheng Chang , Tal Uliel , Eric Bainville , Jeffry E. Gonion , Ali Sazegari
CPC classification number: G06F9/30076 , G06F9/3004 , G06F9/3802
Abstract: In an embodiment, a computation engine may offload a processor (e.g. a CPU) and efficiently perform transcendental functions. The computation engine may implement a range instruction that may be included in a program being executed by the CPU. The CPU may dispatch the range instruction to the computation engine. The range instruction may take an input operand (that is to be evaluated in a transcendental function, for example) and may reference a range table that defines a set of ranges for the transcendental function. The range instruction may identify one of the set of ranges that includes the input operand. For example, the range instruction may output an interval number identifying which interval of an overall set of valid input values contains the input operand. In an embodiment, the range instruction may take an input vector operand and output a vector of interval identifiers.
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公开(公告)号：US10346163B2
公开(公告)日：2019-07-09
申请号：US15800342
申请日：2017-11-01
Applicant: Apple Inc.
Inventor： Eric Bainville , Tal Uliel , Erik Norden , Jeffry E. Gonion , Ali Sazegari
Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.
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公开(公告)号：US20180365007A1
公开(公告)日：2018-12-20
申请号：US15955417
申请日：2018-04-17
Applicant: Apple Inc.
Inventor： Eric Bainville , Ali Sazegari
Abstract: A novel software updating method is provided. A target file is divided into segments, where some segments are updated by patching, while other segments are updated by archiving. The segmentation of the update allows very large files such as DYLD shared caches to be patched in-place, i.e., by using free space available within the file to perform patching rather than requiring enough free space on disk to store both the new version and the old version of the file. The segmentation of the update also allows each segment to be updated individually by the most optimal update method (copy, patch, or archive) so that the size of the update file can be minimized.
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