公开(公告)号：US12294824B2

公开(公告)日：2025-05-06

申请号：US17952016

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： James M. Hollabaugh ,  Antonio R. De Lima Fernandes ,  Calvin M. Ryan ,  Chandrahas Aralaguppe Chandramohan ,  Mitul Mahendrakumar Panchal

IPC: H04R1/10 ,  H02J7/00

Abstract: A case can communicate with one or more earbuds to obtain information related to the earbuds, such as a battery charge level of the earbud. Due to the interface circuits within the case and the earbuds, the case can obtain the information from a power management unit of the earbud without first communicating with a processor (serving as the central processing unit) of the earbud. As a result, the processor can be powered down, i.e., inactive, and the case can still communicate with the earbud. Examples in which the processor can be powered down include when the earbud is in the case and not in use/service by a user, or when the earbud battery charge level is relatively low.

公开(公告)号：US20240038310A1

公开(公告)日：2024-02-01

申请号：US17874100

申请日：2022-07-26

Applicant: Apple Inc.

Inventor： John J. Sullivan ,  James M. Hollabaugh ,  Jason W. Brinsfield ,  Calvin M. Ryan ,  Andreas Adler

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32

CPC classification number: G11C16/30 ,  G11C16/102 ,  G11C16/14 ,  G11C16/32

Abstract: Techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations are disclosed. A power management integrated circuit (PMIC) coupled to a memory circuit with NVM implements the various techniques disclosed. When a power reset signal is asserted to a PMIC, the PMIC may delay initiation of the power reset cycle when it detects that the NVM coupled to the PMIC is active to prevent corruption of the NVM by the power reset cycle. The PMIC may detect the activity level of the NVM based on an activity output signal that indicates whether the NVM is active (e.g., programming or erasing) or inactive.