DELAYED ZERO-OVERHEAD LOOP INSTRUCTION
    1.
    发明申请
    DELAYED ZERO-OVERHEAD LOOP INSTRUCTION 审中-公开
    延迟零循环循环指令

    公开(公告)号:US20170052782A1

    公开(公告)日:2017-02-23

    申请号:US14831955

    申请日:2015-08-21

    Applicant: Apple Inc.

    CPC classification number: G06F9/325 G06F8/443 G06F9/30065

    Abstract: An apparatus may include a counter circuit and an execution unit. The execution unit may be configured to receive and execute a first instruction. The first instruction may include a first number corresponding to a first number of instructions of a plurality of instructions, a second number corresponding to a number of times to execute a subset of the plurality of instructions, and a third number corresponding to a number of instructions in the subset. The execution unit may be further configured to initialize a first count value in the counter circuit to the second number in response to the execution of the first instruction, to execute the first number of the plurality of instructions, and to execute the subset of the plurality of instructions. The counter circuit may be configured to modify the first count value in response to determining a last instruction of the subset has been retired.

    Abstract translation: 装置可以包括计数器电路和执行单元。 执行单元可以被配置为接收和执行第一指令。 第一指令可以包括对应于多个指令的第一数目的指令的第一数字,对应于执行多个指令的子集的次数的第二数字,以及对应于多个指令的第三个数字 在子集中。 执行单元还可以被配置为响应于第一指令的执行而将计数器电路中的第一计数值初始化为第二数量,以执行多个指令的第一数目,并执行多个指令的子集 的指示。 计数器电路可以被配置为响应于确定已经退出的子集的最后指令来修改第一计数值。

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