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    MAPPABLE FILTER FOR NEURAL PROCESSOR CIRCUIT
    2.
    发明申请
    MAPPABLE FILTER FOR NEURAL PROCESSOR CIRCUIT 有权

    公开(公告)号：US20250021808A1

    公开(公告)日：2025-01-16

    申请号：US18903466

    申请日：2024-10-01

    Applicant: Apple Inc.

    Inventor： Waleed ABDULLA ,  Paolo Di Febbo ,  Mohammad Ghasemzadeh ,  Yohan Rajan

    IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

    DYNAMIC VARIABLE BIT WIDTH NEURAL PROCESSOR
    4.
    发明公开
    DYNAMIC VARIABLE BIT WIDTH NEURAL PROCESSOR 审中-公开

    公开(公告)号：US20230206050A1

    公开(公告)日：2023-06-29

    申请号：US18114169

    申请日：2023-02-24

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Waleed Abdulla ,  Chaminda N Vidanagamachchi ,  Yohan Rajan

    IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/063 ,  G06N3/08 ,  G06N3/04

    Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

    Method and device for surfacing physical environment interactions during simulated reality sessions
    5.
    发明授权
    Method and device for surfacing physical environment interactions during simulated reality sessions 有权

    公开(公告)号：US11132053B2

    公开(公告)日：2021-09-28

    申请号：US16650541

    申请日：2018-09-27

    Applicant: Apple Inc.

    Inventor： Yohan Rajan

    IPC: G06K9/00 ,  G06F3/01 ,  G02B27/01 ,  G06F3/16

    Abstract: In one implementation, a method includes: displaying simulated reality (SR) content; determining whether an object in a physical environment satisfies one or more interaction criteria; and changing display of the SR content from a first view to a second view, in response to determining that the object in the physical environment satisfies the one or more interaction criteria, wherein, in the first view, the object in the physical environment is occluded by the SR content, and wherein the second view reduces occlusion of the object in the physical environment by the SR content.

    Method and Device for Surfacing Physical Environment Interactions During Simulated Reality Sessions
    7.
    发明公开
    Method and Device for Surfacing Physical Environment Interactions During Simulated Reality Sessions 审中-公开

    公开(公告)号：US20240061497A1

    公开(公告)日：2024-02-22

    申请号：US18385135

    申请日：2023-10-30

    Applicant: Apple Inc.

    Inventor： Yohan Rajan

    IPC: G06F3/01 ,  G02B27/01 ,  G06F3/16 ,  G06V20/20

    CPC classification number: G06F3/011 ,  G02B27/0101 ,  G02B27/0172 ,  G06F3/017 ,  G06F3/167 ,  G06V20/20 ,  G02B2027/0123

    Abstract: According to various implementations, a method is performed at an electronic device including one or more processors, non-transitory memory, and one or more displays. The method includes, while presenting a virtual environment, via the one or more displays, obtaining a request for interaction from an external source. The virtual environment includes a first plurality of available presentation regions and a second plurality of unavailable presentation regions. The method includes determining whether the request for interaction from the external source satisfies one or more interaction criteria. The method includes presenting, via the one or more displays, an avatar associated with the external source at one of the first plurality of available presentation regions within the virtual environment, in response to determining that the external source satisfies the one or more interaction criteria.

    MAPPABLE FILTER FOR NEURAL PROCESSOR CIRCUIT
    10.
    发明申请
    MAPPABLE FILTER FOR NEURAL PROCESSOR CIRCUIT 有权

    公开(公告)号：US20220108155A1

    公开(公告)日：2022-04-07

    申请号：US17065428

    申请日：2020-10-07

    Applicant: Apple Inc.

    Inventor： Waleed Abdulla ,  Paolo Di Febbo ,  Mohammad Ghasemzadeh ,  Yohan Rajan

    IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

    Abstract: Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

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