公开(公告)号：US12272564B2

公开(公告)日：2025-04-08

申请号：US17456255

申请日：2021-11-23

Applicant: Applied Materials, Inc.

Inventor： Yung-chen Lin ,  Chi-I Lang ,  Ho-yung Hwang

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

公开(公告)号：US20240420953A1

公开(公告)日：2024-12-19

申请号：US18209719

申请日：2023-06-14

Applicant: Applied Materials, Inc.

Inventor： Rui Lu ,  Bo Xie ,  Wei Liu ,  Shanshan Yao ,  Xiaobo Li ,  Jingmei Liang ,  Li-Qun Xia ,  Shankar Venkataraman ,  Chi-I Lang

IPC: H01L21/02

Abstract: Exemplary processing methods may include providing a treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a layer of a silicon-containing material. The methods may include forming inductively-coupled plasma effluents of the treatment precursor. The methods may include contacting the layer of the silicon-containing material with the inductively-coupled plasma effluents of the treatment precursor to produce a treated layer of the silicon-containing material. The contacting may reduce a dielectric constant of the layer of the silicon-containing material.

公开(公告)号：US20240363337A1

公开(公告)日：2024-10-31

申请号：US18139699

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Muthukumar Kaliappan ,  Bo Xie ,  Shanshan Yao ,  Li-Qun Xia ,  Michael Haverty ,  Rui Lu ,  Xiaobo Li ,  Chi-I Lang ,  Shankar Venkataraman

IPC: H01L21/02 ,  C23C16/32 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L21/02167 ,  C23C16/325 ,  C23C16/45542 ,  C23C16/45553 ,  C23C16/45565 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274

Abstract: Semiconductor processing methods are described for forming low-κ dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.

公开(公告)号：US20220367186A1

公开(公告)日：2022-11-17

申请号：US17875535

申请日：2022-07-28

Applicant: Applied Materials, Inc.

Inventor： Nancy Fung ,  Chi-I Lang ,  Ho-yung David Hwang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.

公开(公告)号：US11495461B2

公开(公告)日：2022-11-08

申请号：US16800351

申请日：2020-02-25

Applicant: Applied Materials, Inc.

Inventor： Tejinder Singh ,  Suketu Arun Parikh ,  Daniel Lee Diehl ,  Michael Anthony Stolfi ,  Jothilingam Ramalingam ,  Yong Cao ,  Lifan Yan ,  Chi-I Lang ,  Hoyung David Hwang

IPC: H01L21/033 ,  H01L21/311

Abstract: Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

公开(公告)号：US20250054749A1

公开(公告)日：2025-02-13

申请号：US18366395

申请日：2023-08-07

Applicant: Applied Materials, Inc.

Inventor： Kent Zhao ,  Rui Lu ,  Bo Xie ,  Shanshan Yao ,  Xiaobo Li ,  Chi-I Lang ,  Li-Qun Xia ,  Shankar Venkataraman

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56 ,  H01J37/32

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by a pulsing RF power operating at less than or about 2,000 W. The methods may include forming a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant less than or about 3.0.

公开(公告)号：US20230045689A1

公开(公告)日：2023-02-09

申请号：US17968201

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/027

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US20220199401A1

公开(公告)日：2022-06-23

申请号：US17548689

申请日：2021-12-13

Applicant: Applied Materials, Inc.

Inventor： Yung-Chen Lin ,  Chi-I Lang ,  Ho-yung David Hwang

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/04 ,  C23C16/455

Abstract: Methods for depositing boron-containing films on a substrate are described. The substrate is exposed to a boron precursor and a plasma to form the boron-containing film (e.g., elemental boron, boron oxide, boron carbide, boron silicide, boron nitride). The exposures can be sequential or simultaneous. The boron-containing films are selectively deposited on one material (e.g., SiN or Si) rather than on another material (e.g., silicon oxide).

公开(公告)号：US20210125864A1

公开(公告)日：2021-04-29

申请号：US16662200

申请日：2019-10-24

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/203 ,  H01L21/306 ,  H01L21/3213

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US10954129B2

公开(公告)日：2021-03-23

申请号：US16002218

申请日：2018-06-07

Applicant: Applied Materials, Inc.

Inventor： Takehito Koshizawa ,  Eswaranand Venkatasubramanian ,  Pramit Manna ,  Chi Lu ,  Chi-I Lang ,  Nancy Fung ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  C01B32/28 ,  H01L21/308 ,  C01B32/26 ,  H01L21/311 ,  C01B32/25 ,  H01L21/033 ,  C23C16/26 ,  C23C16/505

Abstract: A method of fabricating a semiconductor structure is described. The method comprises forming at least one mandrel on a substrate, the at least one mandrel comprising a diamond-like carbon and having a top and two opposing sidewalls, the diamond-like carbon comprising at least 40% sp3 hybridized carbon atoms. The mandrel may be used in Self-Aligned Multiple Patterning (SAMP) processes.