公开(公告)号：US12108604B2

公开(公告)日：2024-10-01

申请号：US17479789

申请日：2021-09-20

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Thomas Kwon ,  Mahendra Pakala

IPC: H10B51/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  H01L21/02164 ,  H01L21/02236 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31116

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US11622489B2

公开(公告)日：2023-04-04

申请号：US17476536

申请日：2021-09-16

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L21/28 ,  H01L29/423

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

公开(公告)号：US20230093330A1

公开(公告)日：2023-03-23

申请号：US17994936

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/51

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

公开(公告)号：US11164882B2

公开(公告)日：2021-11-02

申请号：US16783425

申请日：2020-02-06

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L29/423 ,  H01L27/11524 ,  H01L21/28 ,  H01L27/11556

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

公开(公告)号：US11127760B2

公开(公告)日：2021-09-21

申请号：US16265192

申请日：2019-02-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Thomas Kwon ,  Mahendra Pakala

IPC: H01L29/66 ,  H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US11515324B2

公开(公告)日：2022-11-29

申请号：US16720643

申请日：2019-12-19

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L27/1157 ,  H01L29/51 ,  H01L27/11582

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

公开(公告)号：US11384428B2

公开(公告)日：2022-07-12

申请号：US16904396

申请日：2020-06-17

Applicant: Applied Materials, Inc.

Inventor： Mang-Mang Ling ,  Thomas Kwon ,  Jong Mun Kim ,  Chentsau Chris Ying

IPC: C23C16/04 ,  C23C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  C23C14/35 ,  C23C14/04 ,  C23C16/511 ,  C23C14/58 ,  C23C14/06

Abstract: Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.

公开(公告)号：US20220005815A1

公开(公告)日：2022-01-06

申请号：US17476536

申请日：2021-09-16

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11556

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

公开(公告)号：US20200266202A1

公开(公告)日：2020-08-20

申请号：US16783425

申请日：2020-02-06

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.