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    FABRICATING LARGE AREA MULTI-TIER NANOSTRUCTURES
    2.
    发明申请
    FABRICATING LARGE AREA MULTI-TIER NANOSTRUCTURES 审中-公开
    制造大面积多层次的纳米结构

    公开(公告)号：WO2016172116A1

    公开(公告)日：2016-10-27

    申请号：PCT/US2016/028302

    申请日：2016-04-19

    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

    Inventor： SREENIVASAN, Sidlgata, V. ,  JOSEPH, Praveen ,  ABED, Ovadia ,  GRIGAS, Michelle ,  MALLAVARAPU, Akhila ,  AJAY, Paras

    IPC: G21K5/04

    CPC classification number: H01L29/6659 ,  G02B6/124 ,  G03F7/0002 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L28/90 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545

    Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

    Abstract translation: 用于制造和复制用于各种横截面几何形状的自对准多层纳米尺度结构的方法。 这些方法可以利用单个光刻步骤，由此完全消除了在该过程中的对准和覆盖的需要，从而实现接近零重叠误差。 此外，开发了使用这些方法来制造用于主模板，复制模板和基于纳米压印的图案复制的具有各种形状的自对准纳米级多层/多高度图案的技术。 此外，模板可以用于在牺牲聚合物抗蚀剂中图案化多个层次，并且实现层的图案转移到各种基板中以仅使用一个图案化步骤形成完成的大面积纳米电子和纳米光子器件。

    NANOSHAPE PATTERNING TECHNIQUES THAT ALLOW HIGH-SPEED AND LOW-COST FABRICATION OF NANOSHAPE STRUCTURES
    4.
    发明申请
    NANOSHAPE PATTERNING TECHNIQUES THAT ALLOW HIGH-SPEED AND LOW-COST FABRICATION OF NANOSHAPE STRUCTURES 审中-公开
    纳米结构的高速和低成本纳米结构的纳米技术

    公开(公告)号：WO2016065308A1

    公开(公告)日：2016-04-28

    申请号：PCT/US2015/057196

    申请日：2015-10-23

    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

    Inventor： SREENIVASAN, Sidlgata, V. ,  CHERALA, Anshuman ,  CHOPRA, Meghali ,  BONNECAZE, Roger ,  ABED, Ovadia ,  YIN, Bailey ,  MALLAVARAPU, Akhila ,  SINGHAL, Shrawan ,  GAWLIK, Brian

    IPC: C03C15/00

    CPC classification number: H01L21/02521 ,  B81C1/00031 ,  B81C2201/0187 ,  B82Y40/00 ,  G03F7/0002 ,  G11B5/746 ,  H01L21/02381 ,  H01L21/02617 ,  H01L21/3086 ,  H01L29/945 ,  Y10S977/887 ,  Y10S977/888 ,  Y10S977/89

    Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub- 10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.

    Abstract translation: 一种超精密纳米尺寸模板制作方法。 使用电子束光刻在基板上形成具有平滑形状（例如圆形横截面支柱）的结构。 这些结构经历了与导电膜沉积交错的介质的原子层沉积，导致具有超过10nm分辨率的电子束分辨能力的特征的纳米级锐利形状。 使用J-FIL进行纳米级锐利形状的抗蚀刻印刷。 将纳米级尖锐形状蚀刻到基底上的下面的功能膜中，形成具有包括尖角和/或超小间隙的纳米尖锐形状的纳米成形模板。 以这种方式，尖锐的形状可以保持在纳米级。 此外，以这种方式，可以在纳米尺度上发生基本的纳米尺度结构（例如点和线）之外的新颖形状的基于压印的形状控制。

    CATALYST INFLUENCED PATTERN TRANSFER TECHNOLOGY
    6.
    发明申请
    CATALYST INFLUENCED PATTERN TRANSFER TECHNOLOGY 审中-公开

    公开(公告)号：WO2019108366A1

    公开(公告)日：2019-06-06

    申请号：PCT/US2018/060176

    申请日：2018-11-09

    Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

    Inventor： SREENIVASAN, Sidlgata V. ,  MALLAVARAPU, Akhila ,  SINGHAL, Shrawan ,  DUNN, Lawrence R. ,  GAWLIK, Brian

    IPC: H01L21/768 ,  H01L21/78

    Abstract: Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to silicon etching using catalyst influenced chemical etching technology with application to three-dimensional memory architectures and transistors. CICE is a catalyst based etching method that can be used on semiconductors as well as multilayers of the semiconductors. Various embodiments of the CICE process can use a catalyst to etch semiconducting substrates and to fabricate high aspect ratio features. A fabrication tool for this purpose is also disclosed. This shall enable adoption of this technology in making semiconductor devices.

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