公开(公告)号：SG146661A1

公开(公告)日：2008-10-30

申请号：SG2008069346

申请日：2004-09-17

Applicant: BREWER SCIENCE INC

Inventor： BRAKENSIEK NICKOLAS L ,  WASHBURN CARLTON A ,  MURPHY EARNEST C

IPC: H01L20060101 ,  H01L21/027 ,  H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

Abstract: METHOD OF FILLING STRUCTURES FOR FORMING VIA-FIRST DUAL DAMASCENE INTERCONNECTS A method of forming via-first, dual damascene interconnect structures by using a gapfilling, bottom anti- reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing. The solvent is removed from the wafer, and the bottom anti-reflective coating is cured completely by a high- temperature bake. The wafer is then coated with photoresist, and the trench pattern exposed. The bottom anti-reflective coating material used maintains a greater planar topography for trench patterning, eliminates the need for an inorganic light-absorbing material layer on the top of the dielectric stack, protects the bottom of the vias during the trench etch, and prevents the formation of fencing problems by using a solvent to control the thickness in the vias. Figure 3a

公开(公告)号：WO2005029556A2

公开(公告)日：2005-03-31

申请号：PCT/US2004030816

申请日：2004-09-17

Applicant: BREWER SCIENCE INC ,  BRAKENSIEK NICKOLAS L ,  WASHBURN CARLTON A ,  MURPHY EARNEST C

Inventor： BRAKENSIEK NICKOLAS L ,  WASHBURN CARLTON A ,  MURPHY EARNEST C

IPC: H01L20060101 ,  H01L21/027 ,  H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L

CPC classification number: H01L21/76808 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming via-first, dual damascene interconnect structures by using a gapfilling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing. The solvent is removed from the wafer, and the bottom anti-reflective coating is cured completely by a high-temperature bake. The wafer is then coated with photoresist, and the trench pattern exposed. The bottom anti-reflective coating material used maintains a greater planar topography for trench patterning, eliminates the need for an inorganic light-absorbing material layer on the top of the dielectric stack, protects the bottom of the vias during the trench etch, and prevents the formation of fencing problems by using a solvent to control the thickness in the vias.

Abstract translation: 提供了一种通过使用其厚度易于被溶剂控制的间隙填充的底部抗反射涂层材料形成通孔第一双镶嵌互连结构的方法。 在施加到基底之后，底部抗反射涂层通过在低温下烘烤而部分固化。 接下来，将溶剂分配在涂覆的晶片上并使其与涂层接触一段时间。 溶剂以底部抗反射涂层的烘烤温度和溶剂接触时间控制的速率除去底部抗反射涂层，以产生薄的底部抗反射涂层厚度，同时保持电介质上的最佳光吸收性能 叠加。 在该方法的另一可能应用中，可以去除足够的底部抗反射涂层以仅部分填充通孔，以便在后续处理期间保护通孔的底部。 将溶剂从晶片上除去，底部抗反射涂层通过高温烘烤完全固化。 然后用光致抗蚀剂涂覆晶片，暴露沟槽图案。 所使用的底部抗反射涂层材料保持更大的平面形状用于沟槽图案化，消除了在介质叠层的顶部上的无机光吸收材料层的需要，在沟槽蚀刻期间保护通孔的底部，并且防止 通过使用溶剂来控制通孔中的厚度来形成围栏问题。

公开(公告)号：EP1665389A4

公开(公告)日：2008-12-24

申请号：EP04784619

申请日：2004-09-17

Applicant: BREWER SCIENCE INC

Inventor： BRAKENSIEK NICKOLAS L ,  WASHBURN CARLTON A ,  MURPHY EARNEST C

IPC: H01L27/10 ,  H01L20060101 ,  H01L21/027 ,  H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/76808 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming via-first, dual damascene interconnect structures by using a gap-filling, bottom anti-reflective coating material whose thickness is easily controlled by a solvent is provided. After application to a substrate, the bottom anti-reflective coating is partially cured by baking at a low temperature. Next, a solvent is dispensed over the coated wafer and allowed to contact the coating for a period of time. The solvent removes the bottom anti-reflective coating at a rate controlled by the bottom anti-reflective coating's bake temperature and the solvent contact time to yield a bottom anti-reflective coating thickness that is thin, while maintaining optimum light-absorbing properties on the dielectric stack. In another possible application of this method, sufficient bottom anti-reflective coating may be removed to only partially fill the vias in order to protect the bottoms of the vias during subsequent processing. The solvent is removed from the wafer, and the bottom anti-reflective coating is cured completely by a high-temperature bake. The wafer is then coated with photoresist, and the trench pattern exposed. The bottom anti-reflective coating material used maintains a greater planar topography for trench patterning, eliminates the need for an inorganic light-absorbing material layer on the top of the dielectric stack, protects the bottom of the vias during the trench etch, and prevents the formation of fencing problems by using a solvent to control the thickness in the vias.

Abstract translation: 先通孔形成的方法，通过使用间隙填充，底部抗反射涂层材料被提供，其厚度容易被溶剂控制的双镶嵌互连结构。 施加到基片后，将底部抗反射涂层部分地由在低温下烘烤固化。 接着，溶剂被分配在所述涂覆的晶片，并使其接触所述涂层的一段时间。 溶剂移除底部抗反射涂层在由底部抗反射涂层的烘烤温度和溶剂的接触时间，以产生一个底部抗反射涂层的厚度控制的速率做薄，同时保持在所述电介质的最佳光吸收性能 叠加。 在该方法的另一种可能的应用中，足够的底部抗反射涂层可以被去除以仅部分地填充通孔，以保护通孔的底部的后续处理期间。 将溶剂从晶片上去除，底部抗反射涂层完全固化通过高温烘烤呼叫。 然后将晶片涂上光致抗蚀剂，并在沟槽图案露出。 所使用的底层抗反射涂层材料保持为沟槽图案化更大的平面地形，省去了为了在电介质堆叠的顶部无机光吸收材料层的需要，沟槽蚀刻期间保护通孔的底部，并防止 通过使用溶剂来控制在导通孔的厚度形成栅栏的问题。