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公开(公告)号：US07257033B2
公开(公告)日：2007-08-14
申请号：US11084214
申请日：2005-03-17
Applicant: Bin Wang , Chih-Hsin Wang , William T. Colleran
Inventor： Bin Wang , Chih-Hsin Wang , William T. Colleran
IPC: G11C16/04
CPC classification number: G11C16/10
Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.
Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。
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公开(公告)号：US07375398B2
公开(公告)日：2008-05-20
申请号：US11138888
申请日：2005-05-26
Applicant: Bin Wang , Chih-Hsin Wang
Inventor： Bin Wang , Chih-Hsin Wang
IPC: H01L23/62
CPC classification number: H01L29/4983 , H01L29/0653 , H01L29/4916 , H01L29/7833 , H01L29/7835 , H01L29/7836
Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.
Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。
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公开(公告)号：US20060209598A1
公开(公告)日：2006-09-21
申请号：US11084214
申请日：2005-03-17
Applicant: Bin Wang , Chih-Hsin Wang , William Colleran
Inventor： Bin Wang , Chih-Hsin Wang , William Colleran
IPC: G11C16/04
CPC classification number: G11C16/10
Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.
Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。
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公开(公告)号：US20070263456A1
公开(公告)日：2007-11-15
申请号：US11748541
申请日：2007-05-15
Applicant: Bin Wang , Chih-Hsin Wang , William Colleran
Inventor： Bin Wang , Chih-Hsin Wang , William Colleran
IPC: G11C16/04
CPC classification number: G11C16/10
Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.
Abstract translation: NVM阵列包括包括浮动栅极和四晶体管存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。
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公开(公告)号：US08264039B2
公开(公告)日：2012-09-11
申请号：US10952708
申请日：2004-09-28
Applicant: Bin Wang , William T. Colleran , Chih-Hsin Wang
Inventor： Bin Wang , William T. Colleran , Chih-Hsin Wang
IPC: H01L29/78
CPC classification number: H01L29/4983 , H01L29/0653 , H01L29/1045 , H01L29/42368 , H01L29/4916 , H01L29/7835
Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.
Abstract translation: 高压LDMOSFET包括其中形成栅极阱的半导体衬底。 源极阱和漏极阱形成在栅极阱的任一侧上，并且在其内部包括未达到全部深度的绝缘区域。 绝缘层设置在衬底上，覆盖栅极阱以及源极阱和漏极阱的一部分。 导电栅极设置在绝缘层上。 在源阱和排水井附近形成偏置井。 在衬底中形成深阱，使得其在偏压井和浇口井下连通，同时在源井和排水井下方延伸，以避免它们。 偏置井顶部的偏置接触偏压深井，因此井也很好。
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Patent Agency Ranking
公开(公告)号：US20060001050A1
公开(公告)日：2006-01-05
申请号：US11138888
申请日：2005-05-26
Applicant: Bin Wang , Chih-Hsin Wang
Inventor： Bin Wang , Chih-Hsin Wang
IPC: H01L29/745 , H01L21/335
CPC classification number: H01L29/4983 , H01L29/0653 , H01L29/4916 , H01L29/7833 , H01L29/7835 , H01L29/7836
Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.
Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底，衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中，包括第二类型的掺杂植入物，并且适于接收源极接触。 这样，第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方，并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。
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公开(公告)号：US20050258461A1
公开(公告)日：2005-11-24
申请号：US10952708
申请日：2004-09-28
Applicant: Bin Wang , William Colleran , Chih-Hsin Wang
Inventor： Bin Wang , William Colleran , Chih-Hsin Wang
IPC: H01L29/06 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/78
CPC classification number: H01L29/4983 , H01L29/0653 , H01L29/1045 , H01L29/42368 , H01L29/4916 , H01L29/7835
Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.
Abstract translation: 高压LDMOSFET包括其中形成栅极阱的半导体衬底。 源极阱和漏极阱形成在栅极阱的任一侧上，并且在其内部包括未达到全部深度的绝缘区域。 绝缘层设置在衬底上，覆盖栅极阱以及源极阱和漏极阱的一部分。 导电栅极设置在绝缘层上。 在源阱和排水井附近形成偏置井。 在衬底中形成深阱，使得其在偏压井和浇口井下连通，同时在源井和排水井下方延伸，以避免它们。 偏置井顶部的偏置接触偏压深井，因此井也很好。
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公开(公告)号：USD1039353S1
公开(公告)日：2024-08-20
申请号：US29782500
申请日：2021-05-07
Abstract: FIG. 1 is a perspective view of a magnet showing our new design;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
The broken line showing of a magnet is for the purpose of illustrating portions of the article and forms no part of the claimed design. -
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