公开(公告)号：WO2002073582A2

公开(公告)日：2002-09-19

申请号：PCT/US2002/006067

申请日：2002-02-26

Applicant: CANDESCENT TECHNOLOGIES CORPORATION

Inventor： DUNPHY, James, C. ,  HANSEN, Ronald, L. ,  LINDBERG, Brian, E. ,  TRUPPA, Jerome, M. ,  ELLOWAY, Donald, J. ,  AMANIAMPONG, Duke, K.

IPC: G09G3/10

CPC classification number: H01J9/44 ,  G09G3/22 ,  G09G2310/066 ,  H01J2209/0223

Abstract: This writing discloses a method and a circuit for powering-on andpowering-off an FED screen during normal operation to reduce emitter and gate electrode degradation.

Abstract translation: 用于场致发射显示装置的接通和关断元件的电路和方法，以防止发射极（60）和栅电极（50）劣化。 电路（910）包括具有定序器的控制逻辑（916），其在一个实施例中可以使用状态机来实现。 在电源接通时，控制逻辑向向阳极电极（914）供应电压的高电压电源（912）发送使能信号。 此时，低电压电源（918）和驱动电路（920）被禁用。 当从高压电源接收到确认信号时，控制逻辑使能向驱动电路（920）提供电压的低压电源。 当从低电压电源（918）接收到确认信号时，或者可选地，在预定时间段期满之后，控制逻辑（916）然后启用驱动电路（50）和发射极 构成FED装置的行和列的电极（60）。 在断电时，控制逻辑（916）首先禁用低电压电源（918），然后禁用高压电源（912）。

公开(公告)号：EP1364361A2

公开(公告)日：2003-11-26

申请号：EP02725025.7

申请日：2002-02-26

Applicant: Candescent Technologies Corporation

Inventor： DUNPHY, James, C. ,  HANSEN, Ronald, L. ,  LINDBERG, Brian, E. ,  TRUPPA, Jerome, M. ,  ELLOWAY, Donald, J. ,  AMANIAMPONG, Duke, K.

IPC: G09G3/10

CPC classification number: H01J9/44 ,  G09G3/22 ,  G09G2310/066 ,  H01J2209/0223

Abstract: A circuit and method for turning-on and turning-off elements of an field emission display device to protect against emitter electrode(60) and gate electrode(50) degradation. The circuit(910) includes control logic(916) having a sequencer which in one embodiment can be realized using a state machine. Upon power-on, the control logic sends an enable signal to a high voltage power supply (912) that supplies voltage to the anode electrode (914). At this time a low voltage power supply (918) and driving circuitry (920)are disabled. Upon receiving a confirmation signal from the high voltage power supply, the control logic enables the low voltage power supply which supplies voltage to the driving circuitry (920). Upon receiving a confirmation signal from the low voltage power supply (918), or optionally after expiration of a predetermined time period, the control logic (916) then enables the driving circuitry (920) which drives the gate electrodes (50) and the emitter electrodes (60) which make up the rows and columns of the FED device. Upon power down, the control logic (916) first disables the low voltage power supply (918), then the high voltage power supply (912).