公开(公告)号：DE69535164D1

公开(公告)日：2006-09-21

申请号：DE69535164

申请日：1995-10-26

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  HARUMA KAZUHIKO

IPC: H04N7/50 ,  H04N7/26 ,  H04N7/52

Abstract: A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits.

公开(公告)号：DE69526025T2

公开(公告)日：2002-08-22

申请号：DE69526025

申请日：1995-10-26

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  HARUMA KAZUHIKO

IPC: H04N7/26 ,  H04N7/50 ,  H04N7/52 ,  H04N7/24

Abstract: A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits.

公开(公告)号：DE69122647T2

公开(公告)日：1997-02-27

申请号：DE69122647

申请日：1991-03-08

Applicant: CANON KK

Inventor： SHIKAKURA AKIHIRO ,  YAMASHITA SHINICHI

IPC: H03M13/00 ,  H03M13/09

Abstract: In an information signal processing arrangement, an information signal, to which an error detecting code has been added and a part of which other than the error detecting code has been set to a code indicating a predetermined value, is received. Error detection capability is increased by detecting an error in the information signal according to the error detecting code added to the received information signal, and detecting whether or not the part of the information signal set to the predetermined value has changed.

公开(公告)号：DE69027255D1

公开(公告)日：1996-07-11

申请号：DE69027255

申请日：1990-07-11

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  TANAKA MITSUGU

IPC: H04N9/793 ,  H04N9/825 ,  H04N5/92

公开(公告)号：GB2258363B

公开(公告)日：1993-04-28

申请号：GB9219304

申请日：1992-09-11

Applicant: CANON KK

Inventor： KASHIDA MOTOKAZU ,  HOSHI HIDENORI ,  NAGASAWA KENICHI ,  YAMASHITA SHINICHI

IPC: G11B15/467 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/30 ,  H04N5/7826 ,  H04N9/797 ,  H04N9/877 ,  H04N9/888 ,  H04N5/92 ,  G11B20/20

Abstract: An apparatus for reproducing digital information from a recording medium having a plurality of parallel tracks and digital information recorded thereon as n-channel (n being an integer greater than or equal to 2) digital signals. The n-channel digital signals are reproduced by n-reproducing heads. The digital information contained in the reproduced signals is stored in a storage device. Discriminating data is obtained for determining which of the n-channel digital signals reproduced correspond to the reproducing heads. The timing of an access device, accessing the storage device for performing a predetermined processing of the digital signals stored in the storage device relative to the reproducing timing of the digital information reproduced by the n reproducing heads, is controlled in accordance with the discrimination data.

公开(公告)号：DE3911692A1

公开(公告)日：1989-11-02

申请号：DE3911692

申请日：1989-04-10

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  NAGASAWA KENICHI ,  SASATANI TOMOHIKO ,  YAGISAWA TOSHIHIRO

IPC: G11B20/10 ,  G11B20/18 ,  G11B27/00 ,  G11B27/30 ,  G11B27/32 ,  H04N9/797

Abstract: In a digital signal recording apparatus it is possible to input plural kinds of digital information signals having different bit rates from one another. Recording is performed for each data block which includes a predetermined amount of data which includes main data corresponding to the digital information. The ratio of the main data within the data block is switched in accordance with each kind of digital information signal.

公开(公告)号：DE69535164T2

公开(公告)日：2007-06-28

申请号：DE69535164

申请日：1995-10-26

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  HARUMA KAZUHIKO

IPC: H04N7/50 ,  H04N7/26 ,  H04N7/52

Abstract: A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits.

公开(公告)号：DE69523102T2

公开(公告)日：2002-05-02

申请号：DE69523102

申请日：1995-07-18

Applicant: CANON KK

Inventor： SASAKI YOSHIYUKI ,  YAMASHITA SHINICHI

IPC: G11B20/14 ,  H03L7/091 ,  H04N5/93

公开(公告)号：DE3911692C2

公开(公告)日：2001-04-19

申请号：DE3911692

申请日：1989-04-10

Applicant: CANON KK

Inventor： YAMASHITA SHINICHI ,  NAGASAWA KENICHI ,  SASATANI TOMOHIKO ,  YAGISAWA TOSHIHIRO

IPC: G11B20/10 ,  G11B20/18 ,  G11B27/00 ,  G11B27/30 ,  G11B27/32 ,  H04N9/797 ,  G11B5/09

Abstract: In a digital signal recording apparatus it is possible to input plural kinds of digital information signals having different bit rates from one another. Recording is performed for each data block which includes a predetermined amount of data which includes main data corresponding to the digital information. The ratio of the main data within the data block is switched in accordance with each kind of digital information signal.

公开(公告)号：DE69219376T2

公开(公告)日：1997-12-11

申请号：DE69219376

申请日：1992-02-06

Applicant: CANON KK

Inventor： GOHDA MAKOTO ,  YAMASHITA SHINICHI ,  TANAKA YASUYUKI

IPC: G11B5/09 ,  G11B5/66 ,  G11B5/85 ,  G11B20/10 ,  G11B5/68

Abstract: A digital signal to be recorded is converted into a digital signal having a suppressed low-frequency spectrum and having a shortest recording wavelength greater than half an original shortest recording wavelength, and the converted digital signal is recorded on a magnetic recording medium in which a plurality of metal evaporated films having different crystal-growth directions are laminated. The digital signal is reproduced from the magnetic recording medium in which the plurality of metal evaporated films having different crystal-growth directions are laminated. Waveform equalization is performed on the reproduced digital signal, and integration detection is performed on the waveform-equalized digital signal, thereby restoring an original digital signal.