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公开(公告)号：KR830000625A
公开(公告)日：1983-03-18
申请号：KR790001135
申请日：1979-04-11
Applicant: CASIO COMPUTER CO LTD
Inventor： TSUZUKI HANZOU , MIZUNO MAMORU
IPC: G06F15/20
Abstract: The time data processing appts. comprises a time-keeping memory for storing time data, a time-keeping cct. for renewing the time data read out from the time-keeping memory, ! repeatedly at predeted. regular intervals, and a CPU being accessible to the time data in the time-keeping memory while the time-keeping cct. does not make the time-keeping memory accessed. Pref. the time-keeping memory has a memory for storing current time data , one for storing present time data and another for storing flag data representing coincidence or non-coincidence between time data.
Abstract translation: 时间数据处理appts。 包括用于存储时间数据的计时存储器，时间保持cct。 更新从时间记忆读出的时间数据！ 反复在predeted。 定时间隔，并且CPU可以在时间保持存储器中的时间数据访问。 不会使时间记忆存取。 县。 时间存储器具有用于存储当前时间数据的存储器，一个用于存储当前时间数据的存储器，另一个用于存储表示时间数据之间的一致或非重合的标志数据。
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公开(公告)号：KR820001628B1
公开(公告)日：1982-09-11
申请号：KR790001152
申请日：1979-04-12
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
IPC: G06F15/20
Abstract: An electronic timepiece circuit is composed of an oscillator(11), a frequency demultiplier(12) which makes a signal of a second by demultiplying the output reference signal from the oscillator, and a counter which counts the signal of a second from the frequency demultiplier thereby making hours, minutes and seconds. The timepiece data stored in RAM are read to the shift register ebery fixed time interval for arithmetic operations and renewal of the timepiece data. The present data and time adtd are written into RAM l by key operations on the key input device of the main body.
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公开(公告)号：HK61783A
公开(公告)日：1983-12-09
申请号：HK61783
申请日：1983-12-01
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
Abstract: An electronic timepiece circuit is provided with an oscillator for producing a reference signal and a frequency dividing circuit which frequency-divides the reference signal from the oscillator to produce a signal with given time intervals. Clock data stored in the memory is read out therefrom by a timing signal corresponding to the output signal from a given stage of the frequency dividing circuit and is loaded into a shift register where it is stored temporarily. The clock data stored in the memory is read out therefrom at given time intervals by a control signal obtained in accordance with the output signal from a given stage of the frequency dividing circuit, and the read out clock data, together with the clock data read out to the shift register, is subjected to a given operation, with the result that the clock data is updated. The updated clock signal is loaded into the memory by a control circuit.
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公开(公告)号：DE2903680A1
公开(公告)日：1979-08-30
申请号：DE2903680
申请日：1979-01-31
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
Abstract: An electronic timepiece circuit is provided with an oscillator for producing a reference signal and a frequency dividing circuit which frequency-divides the reference signal from the oscillator to produce a signal with given time intervals. Clock data stored in the memory is read out therefrom by a timing signal corresponding to the output signal from a given stage of the frequency dividing circuit and is loaded into a shift register where it is stored temporarily. The clock data stored in the memory is read out therefrom at given time intervals by a control signal obtained in accordance with the output signal from a given stage of the frequency dividing circuit, and the read out clock data, together with the clock data read out to the shift register, is subjected to a given operation, with the result that the clock data is updated. The updated clock signal is loaded into the memory by a control circuit.
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公开(公告)号：DE2906033A1
公开(公告)日：1979-08-23
申请号：DE2906033
申请日：1979-02-16
Applicant: CASIO COMPUTER CO LTD
Inventor： TSUZUKI HANZOU , MIZUNO MAMORU
Abstract: A time data processing apparatus comprises a time-keeping memory for storing time data, a time-keeping circuit for renewing the time data read out from the time-keeping memory and writing the renewed time data into the time-keeping memory, repeatedly at predetermined regular intervals, and a central processing unit being accessible to the time data in the time-keeping memory while the time-keeping circuit does not make the time-keeping memory accessed.
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Patent Agency Ranking
公开(公告)号：CA1117776A
公开(公告)日：1982-02-09
申请号：CA321431
申请日：1979-02-12
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
Abstract: "CLOCK DEVICE" A clock device is provided with an oscillator for producing a reference signal and a frequency dividing circuit which frequency-divides the reference signal from the oscillator to produce a signal with given time intervals. Time data stored in a memory is read out therefrom at given time intervals by a timing signal corresponding to the output signal from a given stage of the frequency dividing circuit and is loaded into a shift register where it is stored temporarily. The time data read out to the shift register, is subjected to an updating operation. The updated clock signal is reloaded into the memory by a control circuit. The temporarily stored time data is also compared with time setting data read out from the memory to provide alarm or timer functions.
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公开(公告)号：CA1105146A
公开(公告)日：1981-07-14
申请号：CA321674
申请日：1979-02-16
Applicant: CASIO COMPUTER CO LTD
Inventor： TSUZUKI HANZOU , MIZUNO MAMORU
Abstract: "TIME DATA PROCESSING APPARATUS" A time data processing apparatus comprises a timekeeping memory for storing time data, a time-keeping circuit for renewing the time data read out from the time-keeping memory and writing the renewed time data into the time-keeping memory, repeatedly at predetermined regular intervals, and a central processing unit being accessible to the time data in the time-keeping memory while the time-keeping circuit does not make the timekeeping memory accessed.
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公开(公告)号：JPH10241055A
公开(公告)日：1998-09-11
申请号：JP5855197
申请日：1997-02-27
Applicant: CASIO COMPUTER CO LTD , KOFU CASIO KK
Inventor： MIZUNO MAMORU , WATANABE YOSHIO , NAKAGOME YOSHIHITO
IPC: G07G1/12
Abstract: PROBLEM TO BE SOLVED: To easily confirm a change of an order at a store by issuing respective slips for a customer and a store in which a fact that they are re-issued slips is expressed in the case that new slips are issued according to addition/ modification of the data of order when the data of order is added/modified after the slips for the customer and the store are issued based on the data of order for one inputted transaction. SOLUTION: The respective slips for the customer and the store are issued by printing and outputting the data of order for the registered one transaction with a printer 8 and after that the data of order for the corresponding transaction is stored and held in RAM 2 by a CPU 1. And when the order is changed after the slips are issued, the slips for the customer and the store in which the fact that they are the re-issued slips is discriminatively expressed are re-issued by changing contents of the RAM 2 and simultaneously printing and outputting the changed contents of the RAM 2 by the CPU 1.
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公开(公告)号：JPS54111243A
公开(公告)日：1979-08-31
申请号：JP1839078
申请日：1978-02-20
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
Abstract: PURPOSE:To make it possible to have access freely to a memory for clocks in the time other than the CPU time counting operation time and perform various arithmetic processings on a basis of time count data by providing the memory for clocks between a clock circuit and a CPU. CONSTITUTION:Clock circuit 9 operates once in a second, and outputs time counting signals TC during the operation. Data bus DB from CPU 1 is disconnected from memory 301 for clocks by this signal TC, and memory 301 for clocks is connected to clock circuit 9. Consequently, the access from CPU 1 to memory 1 for clocks is impossible. Meanwhile, signal TC writes a time counting code in a time counting code write circuit. In case of the access to data of memory 301 for clocks from CPU 1, the time count code on data bus DB is read first; and when no time counting code is confirmed, the access to memory 301 for clocks is permitted. At a power failure time, the potential of the point A in the secondary side of power transformer 13 becomes 0-level rapidly, and as a result, circuit 303 outputs the time counting code to inhibit the access from CPU 1 to memory 301.
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公开(公告)号：JPS54110757A
公开(公告)日：1979-08-30
申请号：JP1733878
申请日：1978-02-17
Applicant: CASIO COMPUTER CO LTD
Inventor： MIZUNO MAMORU , TSUZUKI HANZOU
Abstract: PURPOSE:To simplify the circuit structure without using ROM or the like by memorizing the timing data in the memory unit like RAM or the like and then reading out the memorized timing data to the shift register to carry out the timing action, and at the same time to ensure a quick and assured comparison between the timing data and the time setting data. CONSTITUTION:Divider circuit 12 divides the reference pulse generated at oscillator 11 and obtains the pulses featuring the fixed intervals, and control circuit 18 obtains various kinds of control signals and pulses in accordance with the fixed step of circuit 12. In addition to these units, RAM21 to memorize both the timing data and the time setting data is provided, along with timing register 25 which controls the shift by the timing signal of circuit 18 for the temporary memorization in order to renew the timing data. Thus, the timing data given from RAM21 is read out to register 25 with every time interval controlled by the control signal, and the prescribed operation is carried out to renew the timing data. The renewed data is held at RAM21, and then coincidence circuit 23 gives a comparison between the timing data and the time setting data to perform the prescribed process.
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