公开(公告)号：EP0771007A3

公开(公告)日：1997-11-26

申请号：EP96307293.9

申请日：1996-10-04

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1045

Abstract: A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.

公开(公告)号：EP0697701A2

公开(公告)日：1996-02-21

申请号：EP95401853.7

申请日：1995-08-08

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan

IPC: G11C11/404 ,  G11C11/56

CPC classification number: G11C11/565 ,  G11C11/404 ,  Y10S148/014 ,  Y10S257/903

Abstract: A memory 200 is provided which includes a plurality of bitlines 204, a plurality of wordlines 203, and an array 202 of rows and columns of multi-bit storage locations 201. Each location 201 includes a plurality of cells for storing data presented on an associated bitline 204 in response to a plurality of control signals, at least one of the storage cells of of each storage location 201 receiving a corresponding one of the control signals from an associated wordlines 203.

Abstract translation: 所述存储器包括行和列的阵列耦合到行线的行解码器的几个多比特存储单元（201）。 多比特存储位置具有与/耦合到对应的列线和耦合到对应的行线，并与串联耦合的源极的源极/漏极路径的另一FET的栅极的源极/漏极路径漏极的路径的第一FET 所述第一晶体管和耦合到控制信号源的本地存储位置的栅极。 许多数据存储电容器的（211）被耦合到相应的晶体管的源极/漏极路径和所述控制信号源的本地存储位置可操作以接通该存储到两个电容器之间转移电荷，而行解码器维持 在关断状态的第一晶体管。 数据可以被写入并且由电容器和相关联的列线（204）之间转换电压读出的选定位置（201）的小区（209）的进行。

公开(公告)号：EP0801375A2

公开(公告)日：1997-10-15

申请号：EP97301403.8

申请日：1997-03-04

Applicant: CIRRUS LOGIC, INC.

Inventor： Taylor, Ronald T. ,  Rao, G.R. Mohan ,  Runas, Michael E.

IPC: G09G1/16

CPC classification number: G11C5/066 ,  G09G5/39

Abstract: A single chip frame buffer 302 for use in a display subsystem 300 operable to display images as frames of preselected numbers of pixels, each pixel defined by a preselected number of bits of pixel data. Single chip frame buffer 302 includes an array of memory cells, a number of the memory cells in the array preselected to store pixel data defining a display frame and minimize excess cells. A data port is included having a predetermined number of terminals, the predetermined number of terminals being substantially equal to a number of lines of an associated bus.

Abstract translation: 用于在显示子系统300可操作使用的单芯片帧缓冲器302，以显示图像作为象素的预选号码，由像素数据的比特的预选数量的确定的每个象素的帧。 单片帧缓冲器302包括在存储器单元阵列，多个阵列中的存储器单元的预选存储的像素数据定义一个显示帧和最小化过量的细胞。 数据端口包括具有预定数量的端子，端子基本上等于一个号码相关联的总线的多行的所述预定数目。

公开(公告)号：EP0760512A3

公开(公告)日：1997-09-10

申请号：EP95307744.3

申请日：1995-10-31

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan ,  Sharma, Sudhir ,  Taylor, Ronald Thomas

IPC: G11C5/06

CPC classification number: G11C5/066

Abstract: A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and the multiplexed input/output during a second time period.

公开(公告)号：EP0771007A2

公开(公告)日：1997-05-02

申请号：EP96307293.9

申请日：1996-10-04

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan

IPC: G11C7/00

CPC classification number: G11C7/1036 ,  G11C7/1045

Abstract: A memory 200 including an array 201 of rows and columns of memory cells. Row decoder circuitry 211 is provided for selecting in response to a row address a row in array 201 for access. Column decoder circuitry 205 is provided for selecting at least one location within a first group of columns along the selected row in array 201 in response to a column address. At least one shift register 207 is provided for allowing serial access to one of the cells within a second group of columns along the selected row.

Abstract translation: 存储器200包括存储器单元的行和列的阵列201。 行解码器电路211被提供用于响应于行地址选择阵列201中的行以进行访问。 列解码器电路205被提供用于响应于列地址来选择沿着阵列201中的所选行的第一组列中的至少一个位置。 提供至少一个移位寄存器207，用于允许沿着所选择的行对第二组列中的一个单元进行串行访问。

公开(公告)号：EP0760512A2

公开(公告)日：1997-03-05

申请号：EP95307744.3

申请日：1995-10-31

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan ,  Sharma, Sudhir ,  Taylor, Ronald Thomas

IPC: G11C5/06

CPC classification number: G11C5/066

Abstract: A memory device 200 which includes a multiplexed address/data input/output 230. Circuitry 200 is based around an array 201 of memory cells and includes circuitry 202, 204 for addressing at least one of the cells in the array in response to at least one address bit and circuitry 208, 210, 211, 212 for exchanging data with an addressed one of the cells. Memory device 200 also includes control circuitry 206 operable to pass an address bit presented at the multiplexed input/output to the circuitry for addressing during a first time period and allow for the exchange of data between the circuitry for exchanging and the multiplexed input/output during a second time period.

Abstract translation: 包括多路复用的地址/数据输入/输出230的存储器件200.电路200基于存储器单元的阵列201，并且包括电路202,204，用于响应于至少一个存储单元寻址阵列中的至少一个单元 地址位和电路208,210,211,212，用于与寻址的一个单元交换数据。 存储器装置200还包括控制电路206，其可操作以将在多路复用输入/输出处呈现的地址位传递给用于在第一时间段期间寻址的电路并允许在用于交换的电路与在多路复用输入/输出期间的多路复用输入/输出之间交换数据 第二个时间段。

公开(公告)号：EP0760512B1

公开(公告)日：2001-07-11

申请号：EP95307744.3

申请日：1995-10-31

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan ,  Sharma, Sudhir ,  Taylor, Ronald Thomas

IPC: G11C5/06

CPC classification number: G11C5/066

公开(公告)号：EP0801375A3

公开(公告)日：1999-04-28

申请号：EP97301403.8

申请日：1997-03-04

Applicant: CIRRUS LOGIC, INC.

Inventor： Taylor, Ronald T. ,  Rao, G.R. Mohan ,  Runas, Michael E.

IPC: G09G1/16

CPC classification number: G11C5/066 ,  G09G5/39

Abstract: A single chip frame buffer 302 for use in a display subsystem 300 operable to display images as frames of preselected numbers of pixels, each pixel defined by a preselected number of bits of pixel data. Single chip frame buffer 302 includes an array of memory cells, a number of the memory cells in the array preselected to store pixel data defining a display frame and minimize excess cells. A data port is included having a predetermined number of terminals, the predetermined number of terminals being substantially equal to a number of lines of an associated bus.

公开(公告)号：EP0697701A3

公开(公告)日：1996-12-04

申请号：EP95401853.7

申请日：1995-08-08

Applicant: CIRRUS LOGIC, INC.

Inventor： Rao, G.R. Mohan

IPC: G11C11/404 ,  G11C11/56

CPC classification number: G11C11/565 ,  G11C11/404 ,  Y10S148/014 ,  Y10S257/903

Abstract: A memory 200 is provided which includes a plurality of bitlines 204, a plurality of wordlines 203, and an array 202 of rows and columns of multi-bit storage locations 201. Each location 201 includes a plurality of cells for storing data presented on an associated bitline 204 in response to a plurality of control signals, at least one of the storage cells of of each storage location 201 receiving a corresponding one of the control signals from an associated wordlines 203.