公开(公告)号：JPH0221638A

公开(公告)日：1990-01-24

申请号：JP5949989

申请日：1989-03-10

Applicant: CIRRUS LOGIC INC

Inventor： EICHI RABINDORA ,  SUHASU ESU PATEIRU ,  AANESUTO ESU RIN ,  MAFUDO ASAA ,  DAYAKAA REDEI

IPC: H01L27/118 ,  H01L21/82 ,  H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To achieve high integration by tiling sub-gates and other subfunctional elements in an SLA using a set of static CMOS tile such that individual units can be modified by mass programming technology. CONSTITUTION: Individual tiles of a CMOS cell set are mapped onto one or a plurality of grids of a memory logic array. In an odd row, the grid comprises four horizontal signal wires O, Y, C and U provided on a lower metal film, four vertical signal wires B, G, R and P provided on an upper metal film, and a power supply wire Vdd and an earth wire GND extending along the left and right edges. In an even row, the vertical wire, the power supply wire Vdd and the earth wire GND are reversed. The grid is designed to be superposed on an adjacent grid in the same row while sharing the power supply wire Vdd and the earth wire GND between adjacent grids. According to the method, modification can be facilitated significantly when an existing design is repaired or improved using a software design tool.