公开(公告)号：JPH1097517A

公开(公告)日：1998-04-14

申请号：JP17466197

申请日：1997-06-30

Applicant: CIRRUS LOGIC INC

Inventor： OGLETREE THOMAS

IPC: G06F17/10 ,  G06F7/544

Abstract: PROBLEM TO BE SOLVED: To speed up an operation processing shown by the form of the sum of products by providing a first multiplexer (MUX) giving 2x bit product output and a second multiplexer having output supplying one calculated value. SOLUTION: An inner control circuit 380 receives a discrete operation control value and a BM state control signal from BMMC devices 310-315. The inner control circuit 380 selects i-th input of first MUX 320 corresponding to a booth multiplier BMi by using a first MUX selection bus 382. A PMAA circuit 200 contains second MUX 370. Second MUX 370 has m=four inputs and respective inputs are connected to receive an output signal from one of four accumulator registers 360-363. An outer controller controls the selection bus 371 of second MUX 370 so that the output of ACCI being one of the accumulator registers 360-363 is selected and supplied j-th input of second MUX 370 is selected, and it is outputted through second MUX 370.