公开(公告)号：JPH09231506A

公开(公告)日：1997-09-05

申请号：JP12070796

申请日：1996-05-15

Applicant: CIRRUS LOGIC INC

Inventor： MAAKU ESU SUPAABETSUKU ,  RICHIYAADO TEII BEERENZU

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/02

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of a cross talk phenomenon accompanied with a write VFO frequency by introducing an inter-polating type timing recovery loop into an amplitude read channel. SOLUTION: A frequency synthesizer 52 generates a sampling clock given to a sampling device 24 through a line 54. The sampling clock is also given to a discrete time equalizing filter 26 and an interpolated timing recovery 100. The recovery 100 generates a sampling value 102 interpolated in synchronization with a port rate by interpolating the equalized sampling value 32. A discrete time sequence detector 34 detects a binary sequence 33 estimated from the value 102. The recovery 100 also generates a data clock 104.