公开(公告)号：DE69635887T2

公开(公告)日：2006-08-10

申请号：DE69635887

申请日：1996-12-20

Applicant: COMPAQ COMPUTER CORP

Inventor： KELLY PHILIP C ,  DESCHEPPER TODD J ,  REIF JAMES R

IPC: G06F1/32

公开(公告)号：DE69635887D1

公开(公告)日：2006-05-04

申请号：DE69635887

申请日：1996-12-20

Applicant: COMPAQ COMPUTER CORP

Inventor： KELLY PHILIP C ,  DESCHEPPER TODD J ,  REIF JAMES R

IPC: G06F1/32

公开(公告)号：JPH11328106A

公开(公告)日：1999-11-30

申请号：JP36512198

申请日：1998-12-22

Applicant: COMPAQ COMPUTER CORP

Inventor： REIF JAMES R ,  ALZIEN KHALDOUN ,  MELO MARIA L

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06T1/20 ,  G06T1/00

Abstract: PROBLEM TO BE SOLVED: To improve a memory hit rate and efficiency by an adaptive estima tion read. SOLUTION: A bridge logic unit which connects a CPU bus 103 and a PCI bus is equipped with a CPU interface 204 equipped with a CPU bus interface control unit 302. The control unit 302 fetches one data line from a main memory under the control of a fetch control unit when receiving a 1st read request from a CPU and fetches not only the requested data line, but also a successive data line by estimation when receiving a read request for the successive data line. When the CPU makes a memory read request for a nonsuccessive data line, only the data line is fetched. By this estimation fetching, the memory read efficiency is improved.