公开(公告)号：JPH07202874A

公开(公告)日：1995-08-04

申请号：JP33423094

申请日：1994-12-16

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BUARUTERU BERA ,  ANDOREA FUINOTERO ,  DANIIRO GARUGAANI ,  MARUKO GANDEIINI

IPC: H03L7/087 ,  H04L7/00 ,  H04L7/033 ,  H04L27/227

Abstract: PURPOSE: To prevent spurious locks of a clock signal extraction circuit and to attain stable automatic adjustment of received data by controlling the voltage of a local oscillator using two feedback loops in a receiver. CONSTITUTION: A clock signal generation block in a receiver comprises a voltage controlled oscillator(VCO) and a PLL circuit consisting of master and slave feedback loops. In the main loop, a reference signal generated from a crystal controlled oscillator (XO) is compared with the output of the VCO by a phase/ frequency detector FF and the output of the VCO is allowed to coincide with the reference signal by a low pass filter PB2 to control the VCO. In the slave loop, serial flow of the output signal from the VCO is compared with that of data obtained from a line 6. error pulses V1, D1 are supplied to a low pass filter PB1, the VCO is accurately corrected by an output F1 from the filter PB1 and a recovery clock signal is outputted to an output line 30. Consequently phases and frequency bands between the output signal of the VCO and the reference signal can be accurately synchronized.

公开(公告)号：JPH07335957A

公开(公告)日：1995-12-22

申请号：JP16158495

申请日：1995-06-06

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BUARUTERU BERA ,  PAORO PEREGURIINO

IPC: H01S5/042 ,  H01S5/062 ,  H01S3/096

Abstract: PURPOSE: To provide a circuit which enables a high speed drive of a laser diode and efficiently operates at a speed meeting requirements given by an optical fiber communication system to avoid interference between an optical source drive current and bias current. CONSTITUTION: When a data transmitting source feeds a drive current to the input I of a cascade of CMOS inverters, this cascade can be driven by the cascade of inverters having characteristics about the size of p- and n-type CMOS transistors at a speed enough for the input capacity of transistors SM. When the voltage is at a low logic level on the input I, the gate of MS goes to a high logic level to cut off the p-type transistor and only a bias current fed from MP flows to a terminal L. The current flowing to this terminal L is given by addition of the bias current to a modulating current fed from MM, and both currents depend on a voltage fed to terminals M and P but are mutually independently adjustable.