中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.023 seconds)

    PROCEDE ET SYSTEME POUR LA GENERATION DE PANNES
    2.
    发明专利
    PROCEDE ET SYSTEME POUR LA GENERATION DE PANNES 未知

    公开(公告)号：MA24942A1

    公开(公告)日：2000-04-01

    申请号：MA25705

    申请日：1999-07-26

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELFORTE PIERO ,  CALCAGNO PIERO

    IPC: G01R31/28 ,  G01R31/00

    Abstract: UN PROCÉDÉ POUR LA GÉNÉRATION DE PANNES SUR UNE PLURALITÉ DE MODULES (C1, C2..., C1...CN) D'ÉQUIPEMENTS ÉLECTRONIQUES PRÉVOIT D'ÉQUIPER LESDITS MODULES (C1) DE RESPECTIFS MOYENS DE GÉNÉRATION DE PANNE, ET D'ASSOCIER AUXDITS MODULES (C1) DESDITS RESPECTIVES UNITÉS DE COMMANDES DESDITS RESPECTIFS MOYENS DE GÉNÉRATION DE PANNE. CES UNITÉS DE COMMANDE SONT CAPABLES DE COMANDER LA GÉNÉRATION SÉLECTIVE DE PANNES PAR LES MOYENS DE GÉNÉRATION DE PANNE EN FONCTION DES RESPECTIFS SIGNAUX DE COMMANDE DE GÉNÉRATION DE PANNE. LES DIFFÉRENTES UNITÉS DE COMMANDE ÉTANT RELIÉES ENTRE ELLES PAR L'INTERMÉDIAIRE D'UNE STRUCTURE à BUS, DE PRÉFÉRENCE DU TYPE SÉRIEL ÉQUILIBRÉ. DES MOYENS GÉNÉRATEURS DE SIGAUX DE COMMANDE, SONT PRÉVUS POUR ENVOYER LES SIGNAUX DE COMMANDE DE GÉNÉRATION DE PANNE VERS LES UNITÉS DE COMMANDE à TRAVERS LA STRUCTURE à BUS.

    Programmable time control for logic circuits - has counter dividing elementary clock signals and coupled to ROM
    3.
    发明专利
    Programmable time control for logic circuits - has counter dividing elementary clock signals and coupled to ROM 未知

    公开(公告)号：DE2524129A1

    公开(公告)日：1975-12-04

    申请号：DE2524129

    申请日：1975-05-30

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CALCAGNO PIERO

    IPC: G06F1/04 ,  H03K3/78 ,  H03K3/64 ,  H03K5/15

    Abstract: The programmable time control, for logic circuits, simultaneously generates elementary clock signals (7) of arbitrary complexity. The bit configuration is stored and read out according to a given programmed sequence. The read-out is addressed by a signal (3) derived from a clock signal. A counter frequency divides the clock signal and produces periodic signals with progressively increasing period. A read only memory stores the various configurations of signal bits and redundance bits. A correction circuit (CP) uses the redundance bits to perform a test check on the elementary clock signals. A synchronisation circuit (RU, LT) ensures the sync. parallel emission of the elementary clock signals at given time intervals.

    4.
    发明专利
    未知

    公开(公告)号：DE2514668A1

    公开(公告)日：1975-10-09

    申请号：DE2514668

    申请日：1975-04-04

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CALCAGNO PIERO ,  GARETTI ENZO ,  LOBISCH GUENTER

    IPC: G06F7/76 ,  G06F3/04

    Abstract: For the selective energization of combinations of up to m data outputs of a data concentrator with n data inputs (n > m), the concentrator is provided with n control inputs energizable in various patterns. The concentrator comprises a logic network with an enabling section and a performing section, each in the form of a truncated orthogonal matrix with m rows and n columns of gating circuits. In each matrix the number of gating circuits decreases from n in the first row to (n-m+1) in the last row. The gating circuits of each column of the enabling matrix are connected in parallel to a respective control input whose energization gives rise to an internal activation signal in one of these circuits and simultaneously blocks the circuits of the same row while unblocking those on a diagonal for possible activation by the energization of one of the following control inputs; thus, only one activation signal can come from any row and the number of such activation signals - up to m - depends on the number of energized control inputs. The gating circuits of the performing section consist each of a coincidence (NAND or AND) gate connected on the one hand to an output terminal of the corresponding circuit of the enabling matrix and on the other hand to a data input, the gates of each column being connected to the same data input in parallel; the gates of each row work into a common summing circuit (NAND or OR gate) energizing a respective data output if an activation signal is applied to a gating circuit of that row connected to an energized data input.

    9.
    发明专利
    未知

    公开(公告)号：DE2517525A1

    公开(公告)日：1975-10-30

    申请号：DE2517525

    申请日：1975-04-21

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CALCAGNO PIERO ,  GARETTI ENZO

    IPC: H04Q11/04 ,  H04Q1/38

    Abstract: A call monitor for a telephone exchange, including a processor intervening in the establishment of a connection between associated line links with the aid of a switching network, comprises a first memory storing information about each line link and a second memory containing codes that identify all possible states of a connection of interest to the processor along with all intervening conditions termed evolutions. During a time slot allocated to a particular line link, a multibit comparator receives data from the first memory concerning a connection involving that line link, along with updating information from the line link itself, on one set of inputs and further receives, on another set of inputs, a succession of evolutionary codes read out from the second memory until a match is detected; the read-out is then terminated and an instruction, if required, is sent to the processor and/or to the switching network.

Patent Agency Ranking