公开(公告)号：US3887798A

公开(公告)日：1975-06-03

申请号：US42513273

申请日：1973-12-17

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： DEVINCENTIIS GIROLAMO ,  LUVISON ANGELO

IPC: G06F1/025 ,  H03K13/24

CPC classification number: G06F1/0255

Abstract: To generate pulse trains corresponding to the binary representation of numbers in the so-called Walsh code, the numbers ranging from 1 to m-1 where m 2k 1, a logic network RC1 with k+1 inputs and m outputs converts a selected binary number into the equivalent Walsh function whose bits are stored on associate flip-flops 501 - 516 forming respective stages of a dynamic memory. Another logic network RC2 determines the highestranking finite bit (1) of the selected binary number and, according to the rank thereof, selects one of k+1 subharmonically related pulse frequencies in the output of a frequency divider to step the dynamic memory at a cadence corresponding to that rank and to read out in series the contents of a corresponding number of pairs of memory stages, representing the stored Walsh function, the read-out recurring continuously until the next selection as the stored bits are recirculated in the memory 501 516.

Abstract translation: 为了产生对应于所谓的沃尔什码中的数字的二进制表示的脉冲串，从1到m-1的数字，其中m = 2k + 1，具有k + 1个输入和m个输出的逻辑网络RC1转换 将选择的二进制数转换成等效的沃尔什函数，其比特存储在形成动态存储器的各个阶段的关联触发器501-516上。 另一个逻辑网络RC2确定所选二进制数的最高排位有限位（1），并且根据其等级，在分频器的输出中选择k + 1次谐波相关的脉冲频率中的一个，以将动态存储器 与该等级对应的节奏，并连续地读出表示所存储的沃尔什函数的相应数量的存储器级对的内容，连续读出循环，直到下一个选择作为存储的比特在存储器501中再循环 - 516。