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    1.
    发明专利
    未知

    公开(公告)号：DK13482A

    公开(公告)日：1982-07-16

    申请号：DK13482

    申请日：1982-01-14

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： BELFORTE P ,  BONDONNO M ,  GARETTI E ,  GUASCHINO G ,  PILATI L

    IPC: H04Q3/545 ,  H04Q11/04 ,  H04Q

    Abstract: Interconnection unit equipped with a microprocessor- controlled unit and auxiliary circuits specialized in diagnostic, allowing the functions of diagnostic, trouble localization and reconfiguration to be carried out by the single building blocks, without requiring the generation of artificial test traffic.

    2.
    发明专利
    未知

    公开(公告)号：BR7901391A

    公开(公告)日：1979-10-02

    申请号：BR7901391

    申请日：1979-03-07

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： MANFREDDI R ,  GARETTI E

    IPC: G06F12/16 ,  G06F3/00 ,  G06F11/10 ,  G11C19/28 ,  G11C27/04 ,  H04Q3/545 ,  G06F9/06 ,  G11C9/06

    Abstract: A stored-program control system for a telephone exchange or the like comprises processing units coupled to several main memories and to several mass memories. Each mass memory includes one or more memory modules each with one or more rows of shift registers of the charge-coupled type, operating in a serial-parallel-serial mode, and a control module equipped with a self-correcting logic and a microprogrammed time base.

    3.
    发明专利
    未知

    公开(公告)号：IT1011782B

    公开(公告)日：1977-02-10

    申请号：IT6831174

    申请日：1974-04-26

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CALCAGNO P ,  GARETTI E

    IPC: H04Q11/04 ,  H04M

    Abstract: A call monitor for a telephone exchange, including a processor intervening in the establishment of a connection between associated line links with the aid of a switching network, comprises a first memory storing information about each line link and a second memory containing codes that identify all possible states of a connection of interest to the processor along with all intervening conditions termed evolutions. During a time slot allocated to a particular line link, a multibit comparator receives data from the first memory concerning a connection involving that line link, along with updating information from the line link itself, on one set of inputs and further receives, on another set of inputs, a succession of evolutionary codes read out from the second memory until a match is detected; the read-out is then terminated and an instruction, if required, is sent to the processor and/or to the switching network.

    4.
    发明专利
    未知

    公开(公告)号：BE874402A

    公开(公告)日：1979-06-18

    申请号：BE193654

    申请日：1979-02-23

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： GARETTI E ,  MANFREDDI R

    IPC: G06F12/16 ,  G06F3/00 ,  G06F11/10 ,  G11C19/28 ,  G11C27/04 ,  H04Q3/545 ,  G06F

    Abstract: A stored-program control system for a telephone exchange or the like comprises processing units coupled to several main memories and to several mass memories. Each mass memory includes one or more memory modules each with one or more rows of shift registers of the charge-coupled type, operating in a serial-parallel-serial mode, and a control module equipped with a self-correcting logic and a microprogrammed time base.

    9.
    发明专利
    未知

    公开(公告)号：BR7903809A

    公开(公告)日：1980-02-05

    申请号：BR7903809

    申请日：1979-06-15

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： GARETTI E ,  MANFREDI R ,  BERNARDINI V

    IPC: G06F12/16 ,  G06F3/00 ,  G06F11/10 ,  G11C19/28 ,  G11C29/00 ,  G11C9/06

    Abstract: Self-correcting, solid-state mass-memory, organized by bits and with reconfiguration capability for a stored program control system, comprising a processing system interfaced towards the mass memory through a controller, said memory consisting of one or a plurality of memory modules and a control module at least, comprising a time base which generates timing and control signals for memory operation, with shape and period variable according to the operation, an addressing control circuit which generates the addresses for memory reading and writing, input-output means which send the data towards the memory or the controller and a self-correcting logic which controls the right operation of the memory, corrects and signals to the controller the possible memory errors, said memory being characterized in that each memory module [ME(1)...ME(p); ME(1)...ME(p + 1); ME(1)...ME(x)] is intended to store a bit of a plurality of words consisting of information and redundancy bits to be used for self-correction operations and comprises:… - a plurality of memory integrated circuits (AC1...AC32) obtained by charge-coupled technology and consisting of blocks of shift registers organized in serial-parallel-serial configuration, each block being able to be addressed randomly and at the same time as the blocks of equal position in all the corresponding circuits of all the memory modules and containing a plurality of cells to be addressed in sequence;… - data input-autput means (RT1; RT1A; RT1B; RT1C; LM2);… - means (A1, A2, DE1, A!, A2, DE1, LM1) for receiving from the control module (MC) or each control module (MCA, MCB, MCC) and sending to the integrated circuits (AC) of the memory module the timing, addressing and control signals.

    10.
    发明专利
    未知

    公开(公告)号：SE409158B

    公开(公告)日：1979-07-30

    申请号：SE7504818

    申请日：1975-04-25

    Applicant: CSELT CENTRO STUDI LAB TELECOM

    Inventor： CALCAGNO P ,  GARETTI E

    IPC: H04Q11/04 ,  H04Q1/38 ,  H04Q3/04

    Abstract: A call monitor for a telephone exchange, including a processor intervening in the establishment of a connection between associated line links with the aid of a switching network, comprises a first memory storing information about each line link and a second memory containing codes that identify all possible states of a connection of interest to the processor along with all intervening conditions termed evolutions. During a time slot allocated to a particular line link, a multibit comparator receives data from the first memory concerning a connection involving that line link, along with updating information from the line link itself, on one set of inputs and further receives, on another set of inputs, a succession of evolutionary codes read out from the second memory until a match is detected; the read-out is then terminated and an instruction, if required, is sent to the processor and/or to the switching network.

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