公开(公告)号：US3914695A

公开(公告)日：1975-10-21

申请号：US48699974

申请日：1974-07-10

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： GIUSTO PIETRO PORZIO

IPC: H04L27/20 ,  H04B1/04

CPC classification number: H04L27/2071

Abstract: A binary data stream of cadence f to be transmitted by PSK (phase-shift keying) modulation is split into two pulse sequences, composed of alternate bits of that data stream, which are translated into 180* phase shifts of respective sinusoidal carrier waves in quadrature with each other, the frequency f of the two carrier waves being the reciprocal of the pulse width 2/f of the two pulse sequences in a specific instance. A pair of interleaved trains of trigger pulses, each coinciding with the zero crossings of a respective carrier wave, enable the operation of associated phase shifters - in response to amplitude changes of the respective pulse sequences - only at a peak of a carrier wave in trailing position or at a zero crossing of a carrier wave in leading position, thereby minimizing the amplitude excursions occurring upon a subsequent passage of the combined carrier waves through a band-pass filter or other network of limited bandwidth.

Abstract translation: 要通过PSK（相移键控）调制发送的节奏f的二进制数据流被分为由数据流的交替位组成的两个脉冲序列，它们被转换成相位正交载波的180度相移 彼此之间，两个载波的频率f是特定情况下两个脉冲序列的脉冲宽度2 / f的倒数。 触发脉冲的一对交错列，每一个与相应载波的过零点相重合，使得相关联的移相器能够响应于相应脉冲序列的幅度变化而仅在后沿中的载波的峰值处操作 位置或在前导位置处的载波的零交叉处，从而最小化在组合的载波通过带通滤波器或其他有限带宽的网络的后续通过时发生的振幅偏移。

公开(公告)号：IT1145719B

公开(公告)日：1986-11-05

申请号：IT6846281

申请日：1981-11-12

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： GIUSTO PIETRO PORZIO

IPC: H04L27/38 ,  H04L27/227 ,  H03C

Abstract: Circuit recovering the carrier of a signal, amplitude and phase modulated by digital signals, that estimates the phase error of the recovered carrier by the comparison made between the base-band components of the demodulated signal and suitable decision thresholds. The comparison is made at the decision instant generally used to estimate the transmitted digital symbols.

公开(公告)号：IT1128766B

公开(公告)日：1986-06-04

申请号：IT6753080

申请日：1980-04-04

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： GIUSTO PIETRO PORZIO

IPC: H04J7/00 ,  H04L7/06 ,  H04L

Abstract: A stream of digital symbols with three or more distinct amplitude levels, organized in a recurrent frame of N symbol periods, carries supplemental information in the form of a binary word of k bits per frame, with k substantially less than the probable minimum number of modulable waveforms, i.e. symbols of the lowest or the highest normal level. At a transmitting end of a signal path, the binary word is superimposed upon a group of k consecutive modulable waveforms at the beginning of each outgoing frame, with bits of logical value "1" indicated by a supermodulation of corresponding modulable waveforms to raise or lower their amplitudes to an extra-high or an extra-low level; the first and the last bit of this word have invariably the value "1". At a receiving end, a cyclic counter CL4 stepped by extracted clock pulses establishes a recurrent incoming frame of normally N symbol periods while a dead-end counter CC2 registers the first k modulable symbols of such frame and thus determines a recovery interval for the demodulation of their supplemental bits, followed by a redundancy interval in which no supermodulated waveforms are expected to occur in steady-state operation. A logic network PP counts the number of supermodulated waveforms detected in various sections of the redundancy interval and compares that number with the number of "1" bits carried by the first and kth modulable waveforms of the recovery interval; if this comparison reveals a disalignment between the outgoing and incoming frames, the logic network temporarily modifies the operating cycle of the cyclic counter to realign the two frames.

公开(公告)号：IT8168462D0

公开(公告)日：1981-11-12

申请号：IT6846281

申请日：1981-11-12

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： GIUSTO PIETRO PORZIO

IPC: H04L27/38 ,  H04L27/227 ,  H03C

Abstract: Circuit recovering the carrier of a signal, amplitude and phase modulated by digital signals, that estimates the phase error of the recovered carrier by the comparison made between the base-band components of the demodulated signal and suitable decision thresholds. The comparison is made at the decision instant generally used to estimate the transmitted digital symbols.

公开(公告)号：IT8067530D0

公开(公告)日：1980-04-04

申请号：IT6753080

申请日：1980-04-04

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： GIUSTO PIETRO PORZIO

IPC: H04J7/00 ,  H04L7/06 ,  H04L

Abstract: A stream of digital symbols with three or more distinct amplitude levels, organized in a recurrent frame of N symbol periods, carries supplemental information in the form of a binary word of k bits per frame, with k substantially less than the probable minimum number of modulable waveforms, i.e. symbols of the lowest or the highest normal level. At a transmitting end of a signal path, the binary word is superimposed upon a group of k consecutive modulable waveforms at the beginning of each outgoing frame, with bits of logical value "1" indicated by a supermodulation of corresponding modulable waveforms to raise or lower their amplitudes to an extra-high or an extra-low level; the first and the last bit of this word have invariably the value "1". At a receiving end, a cyclic counter CL4 stepped by extracted clock pulses establishes a recurrent incoming frame of normally N symbol periods while a dead-end counter CC2 registers the first k modulable symbols of such frame and thus determines a recovery interval for the demodulation of their supplemental bits, followed by a redundancy interval in which no supermodulated waveforms are expected to occur in steady-state operation. A logic network PP counts the number of supermodulated waveforms detected in various sections of the redundancy interval and compares that number with the number of "1" bits carried by the first and kth modulable waveforms of the recovery interval; if this comparison reveals a disalignment between the outgoing and incoming frames, the logic network temporarily modifies the operating cycle of the cyclic counter to realign the two frames.