公开(公告)号：JPH02150140A

公开(公告)日：1990-06-08

申请号：JP25801489

申请日：1989-10-04

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： KARURO DEMICHIERISU ,  PAORO MATOONE ,  ARETSUSANDORO ZAPARORUTO

IPC: H04J3/24 ,  H04L12/56

Abstract: PURPOSE: To improve system performance in simple constitution by performing access from an arbitrating circuit and a distributed circuit network to a common control circuit. CONSTITUTION: A bi-directional asynchronous multiplexer 1 is connected with blocks TMA in the same number for executing a high speed cell processing, with an input bus 2 of a multiple switching circuit network NWD under the control of an arbitrating circuit ARB and a first bus 7, and through a distributed circuit network DIS and a second bus 4 with an output bus 8 of a circuit network. A common control circuit CON is connected through a third bus 3 with each block TMA which performs access through first connection 5 and the arbitrating circuit ARB to the switching circuit network NWD. Then, on the contrary, the circuit network NWD performs access through the distributed circuit network DIS and second connection 6 to the common control circuit CON. Thus, system performance is improved in simple constitution.