公开(公告)号：JP2011210939A

公开(公告)日：2011-10-20

申请号：JP2010076966

申请日：2010-03-30

Applicant: Casio Computer Co Ltd ,  カシオ計算機株式会社

Inventor： KONO ICHIRO ,  MASUDA KAZUHIRO ,  KURIHARA MITSUHIKO

IPC: H01L23/12

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device that prevents a migration phenomenon of metal, and to provide a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device 1 includes: a plurality of re-wiring lines 19 formed on an upper surface of a semiconductor substrate 11 having a plurality of connection terminals 12 and each having one end connected to a connection terminal 12; a plurality of columnar electrodes 21 each formed on an other upper surface of a re-wiring line 19; an insulating film 15 covering at least side faces of the re-wiring lines 19 and side faces of the columnar electrodes 21 and exposing upper surfaces of the columnar electrodes 21; and a sealing film 22 which seals a surface of the insulating film 15 and exposing the upper surfaces of the columnar electrodes 21. The insulating film 15 is formed by applying and curing a resin material.

Abstract translation: 要解决的问题：提供一种廉价的半导体装置，其防止金属的迁移现象，并提供制造半导体器件的方法。解决方案：半导体器件1包括：多个重新布线19，形成在上部 具有多个连接端子12并且各自具有连接到连接端子12的一端的半导体基板11的表面; 多个柱状电极21，各自形成在再布线19的另一个上表面上; 绝缘膜15，其覆盖重新布线19的至少侧面和柱状电极21的侧面，并且暴露柱状电极21的上表面; 以及密封绝缘膜15的表面并暴露柱状电极21的上表面的密封膜22.绝缘膜15通过施加和固化树脂材料而形成。

公开(公告)号：JP2011082408A

公开(公告)日：2011-04-21

申请号：JP2009234819

申请日：2009-10-09

Applicant: Casio Computer Co Ltd ,  カシオ計算機株式会社

Inventor： MASUDA KAZUHIRO

IPC: H01L23/12

CPC classification number: H01L2224/11 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To prevent a crack of a solder ball generated due to a step part between the upper surface of a sealing film and that of an electrode for external connection.
SOLUTION: The upper surface 16a of a sealing film 16 is formed at a high position relative to the upper surfaces 20a of electrodes 20 for external connection, and step parts are formed at boundaries between both the members. A buffer layer 31 is formed on the upper surface 16a of the sealing film 16 and on side faces of the step parts with the electrodes 20 for external connection on the sealing film 16. Regions of the buffer layer 31 corresponding to the step parts are formed into inclined surfaces 31b. Solder balls jointed to the upper surfaces of the electrodes 20 for external connection are formed tightly on the inclined surfaces 31b of the buffer layer 31.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了防止由于密封膜的上表面和用于外部连接的电极的台阶部分之间产生的焊球的裂纹。 解决方案：密封膜16的上表面16a形成在相对于用于外部连接的电极20的上表面20a的高位置处，并且步骤部分形成在两个构件之间的边界处。 缓冲层31形成在密封膜16的上表面16a上，在台阶部分的侧面上形成有密封膜16上的外部连接用电极20。形成与台阶部对应的缓冲层31的区域 倾斜面31b。 紧贴在缓冲层31的倾斜面31b上的与外部连接的电极20的上表面接合的焊球形成为：（C）2011，JPO＆INPIT

公开(公告)号：JP2010192818A

公开(公告)日：2010-09-02

申请号：JP2009037971

申请日：2009-02-20

Applicant: Casio Computer Co Ltd ,  カシオ計算機株式会社

Inventor： MASUDA KAZUHIRO

IPC: H01L23/12

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor wafer that is hardly warped when curing a sealing film made from liquid resin in the manufacturing of a semiconductor device, side of whose silicon substrate being covered with a side protective film made of resin. SOLUTION: A sealing film 11 made from epoxy resin is coated all aver a semiconductor wafer 21 and cured. Then, the sealing film 11 and the semiconductor wafer 21 at a portion corresponding to a dicing street 22 are subjected to full cut and a groove 25 is formed. Next, dicing tape 23 is pulled and extended in the circumference direction and the groove 25 is widened according to the extension. Next, a side protective film made from room temperature curable resin is formed in the widened groove 25. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供在半导体器件的制造中固化由液体树脂制成的密封膜时难以翘曲的半导体晶片，其硅衬底的侧面被由树脂制成的侧保护膜覆盖。 解决方案：将由环氧树脂制成的密封膜11全部涂覆在半导体晶片21上并固化。 然后，将密封膜11和对应于切割街道22的部分的半导体晶片21进行全切割，并形成凹槽25。 接下来，切割带23沿周向被拉伸并且沿着延伸方向延伸槽25。 接下来，在加宽槽25中形成由室温固化树脂制成的侧保护膜。版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009212271A

公开(公告)日：2009-09-17

申请号：JP2008053082

申请日：2008-03-04

Applicant: Casio Comput Co Ltd ,  カシオ計算機株式会社

Inventor： MASUDA KAZUHIRO

IPC: H01L23/12 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To make it hard for a film having a low dielectric constant to be peeled in a semiconductor device having a silicon substrate and a low-dielectric-constant film wiring laminate structure portion comprising a laminate structure of a silicon substrate, and the film having the low dielectric constant and wiring provided on the silicon substrate. SOLUTION: The low-dielectric-constant film wiring laminate structure portion 3 comprising the laminate structure of the film 4 having the low dielectric constant and wiring 5 is provided in a region except a peripheral portion on an upper surface of the silicon substrate 1. A first passivation film 7 is provided on an upper surface of the low-dielectric-constant film wiring laminate structure portion 3. Then the first passivation film 7 and a side surface of the low-dielectric-constant film wiring laminate structure portion 3 are covered with a second passivation film 9. Consequently, the film 4 having the low dielectric constant has a hard-to-peel structure. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了使具有低介电常数的膜在具有硅衬底的半导体器件和具有硅的层叠结构的低介电常数膜布线层叠结构部分上被剥离是困难的 衬底，并且具有低介电常数的膜和设置在硅衬底上的布线。 解决方案：包括具有低介电常数的膜4和布线5的层压结构的低介电常数膜布线层叠结构部分3设置在除了硅衬底的上表面上的周边部分之外的区域中 第一钝化膜7设置在低介电常数薄膜布线层叠结构部分3的上表面上。然后，第一钝化膜7和低介电常数膜布线层叠结构部分3的侧表面 被第二钝化膜9覆盖。因此，具有低介电常数的膜4具有难以剥离的结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2012028492A

公开(公告)日：2012-02-09

申请号：JP2010164754

申请日：2010-07-22

Applicant: Casio Comput Co Ltd ,  カシオ計算機株式会社

Inventor： MASUDA KAZUHIRO

IPC: H01L23/12

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of buffering stress acted between the semiconductor device and a circuit substrate, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device 1 comprises a semiconductor substrate 11 having a connection pad 12, a buffer layer 14A provided at a part on the semiconductor substrate 11, an insulation film 14B provided on the semiconductor substrate 11 including the buffer layer 14A and having an opening 14a exposing the connection pad 12, a wiring 15 provided so as to connect to the connection pad 12 and having a land on the insulation film 14B in an area corresponding to the buffer layer 14A, and an external connection electrode 21 provided on the land.

Abstract translation: 要解决的问题：提供能够缓冲在半导体器件和电路基板之间作用的应力的半导体器件以及半导体器件的制造方法。 解决方案：半导体器件1包括具有连接焊盘12的半导体衬底11，设置在半导体衬底11的一部分的缓冲层14A，设置在包括缓冲层14A的半导体衬底11上的绝缘膜14B和 具有暴露连接焊盘12的开口14a，设置成连接到连接焊盘12并且在与缓冲层14A相对应的区域中的绝缘膜14B上具有焊盘的布线15以及设置在其上的外部连接电极21 那片土地。 版权所有（C）2012，JPO＆INPIT