公开(公告)号：US20010013630A1

公开(公告)日：2001-08-16

申请号：US09756981

申请日：2001-01-09

Applicant: Chromux Technologies, Inc.

Inventor： Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park ,  Sangchul Lee

IPC: H01L021/00

CPC classification number: B81B3/0086 ,  B81B2203/0136 ,  B81B2203/0307 ,  B81B2203/04

Abstract: An electrical isolation method for silicon microelectromechanical systems provides trenches filled with insulation layers that support released silicon structures. The insulation layer that fills the trenches passes through the middle portion of the electrodes, anchors the electrodes to the silicon substrate and supports the electrode. The insulation layers do not attach the electrode to the sidewalls of the substrate, thereby forming an electrode having an nullislandnull shape. Such an electrode is spaced far apart from the adjacent walls of the silicon substrate providing a small parasitic capacitance for the resulting structure. The isolation method is consistent with fabricating a complex structure or a structure with a complicated electrode arrangement. Furthermore, the structure and the electrode are separated from the silicon substrate in a single release step. Additionally, a metal layer is deposited on the surfaces of the structure and electrodes without using separate photolithography and etching steps.

Abstract translation: 用于硅微机电系统的电隔离方法提供填充有支撑释放的硅结构的绝缘层的沟槽。 填充沟槽的绝缘层通过电极的中间部分，将电极固定到硅衬底并支撑电极。 绝缘层不将电极附着到基板的侧壁，从而形成具有“岛”形状的电极。 这样的电极与硅衬底的相邻壁间隔得很远，为所得到的结构提供了小的寄生电容。 隔离方法与制造具有复杂电极布置的复杂结构或结构一致。 此外，在单个释放步骤中，结构和电极与硅衬底分离。 此外，金属层沉积在结构和电极的表面上，而不使用单独的光刻和蚀刻步骤。

公开(公告)号：US20020001871A1

公开(公告)日：2002-01-03

申请号：US09885832

申请日：2001-06-19

Applicant: Chromux Technologies, Inc.

Inventor： Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

IPC: H01L021/00 ,  H01L021/76

CPC classification number: B81C1/0019 ,  B81C2201/0178 ,  H01L21/764

Abstract: An isolation method for a single crystalline silicon microstructure using a triple layer structure is disclosed. The method includes forming the triple layer composed of an insulation layer formed over an exposed surface of the silicon microstructure, a conductive layer formed over the entire insulation layer, and a metal layer formed over a top portion of the microstructure; and partially etching the conductive layer to form electrical isolation between parts of the microstructure. The method does not require a separate photolithography process for isolation, and can be effectively applied to microstructures having high aspect ratios and narrow trenches. Also disclosed are single crystalline silicon microstructures having a triple layer isolation structure formed using the disclosed method.

Abstract translation: 公开了使用三层结构的单晶硅微结构的隔离方法。 该方法包括形成由在硅微结构的暴露表面上形成的绝缘层，形成在整个绝缘层上的导电层和形成在微结构的顶部上的金属层构成的三层; 并部分地蚀刻导电层以在微结构的各部分之间形成电隔离。 该方法不需要用于隔离的单独的光刻工艺，并且可以有效地应用于具有高纵横比和窄沟槽的微结构。 还公开了具有使用所公开的方法形成的三层隔离结构的单晶硅微结构。