公开(公告)号：US20160080865A1

公开(公告)日：2016-03-17

申请号：US14507372

申请日：2014-10-06

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson

IPC: H04R3/04 ,  H03G3/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

Abstract translation: 根据本公开的实施例，控制电路可以被配置为响应于在具有模拟路径部分的信号路径的增益模式和数字信号路径部分之间切换的指示，切换模拟的可选择的模拟增益 在第一模拟增益和第二模拟增益之​​间的路径部分，在第一数字增益和第二数字增益之间切换数字信号路径部分的可选数字增益，其中第一模拟增益和第一数字增益的乘积近似 等于第二模拟增益和第二数字增益的乘积，并且作为信号路径的增益模式之间的切换的结果，控制信号路径的模拟响应以减少存在于输出信号中的音频伪像的出现。 信号路径可以具有模拟路径部分和数字信号路径部分。 数字部分可以具有可选择的数字控制的增益，并且可以被配置为将数字音频输入信号转换成符合可选数字控制的增益的模拟输入信号，数字信号路径部分包括调制器，包括前向路径和 反馈路径。 正向路径可以包括环路滤波器，用于响应于数字音频输入信号和反馈信号产生经滤波的信号，响应于经滤波的信号产生量化信号的量化器，以及第一增益元件，被配置为将可选择的数字 - 控制增益到正向路径内的信号。 反馈路径可以被配置为响应于量化信号产生反馈信号，反馈路径包括具有与可选数字控制增益成反比的增益的第二增益元件。

公开(公告)号：US09214948B2

公开(公告)日：2015-12-15

申请号：US14255912

申请日：2014-04-17

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Xin Zhao ,  Xiaofan Fei

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/002 ,  H03M1/0809 ,  H03M1/181 ,  H03M1/36

Abstract: A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

Abstract translation: 用于模数转换器（ADC）的比较器跟踪方案可以通过随时间变化多个比较器供电以将模拟输入信号转换为数字输出信号来实现动态窗口尺寸。 比较器跟踪方案可以例如在耦合到ADC中的多个比较器的控制器中实现。 例如，控制器可以确定ADC的窗口大小并确定ADC的窗口位置。 然后，控制器可以在以窗口位置为中心并且具有窗口大小的宽度的窗口内激活ADC的比较器。 控制器可以通过分析滤波器的输出来确定窗口大小。 当滤波器输出指示快速变化的模拟输入信号时，控制器可以动态增加ADC的窗口大小，这可能会增加多个比较器上电。

公开(公告)号：US09853539B1

公开(公告)日：2017-12-26

申请号：US14243261

申请日：2014-04-02

Applicant: Cirrus Logic, Inc.

Inventor： Xin Zhao ,  Ku He ,  Xiaofan Fei

IPC: H02M3/156 ,  H02M3/04

CPC classification number: H02M3/04 ,  H02M3/156 ,  H02M2001/0009

Abstract: A switch control circuit may be utilized for a sequence of switching events occurring in an order of a first event, a second event, a third event, and a fourth event: the first event to activate the first switch and deactivate the second switch wherein an inductor current increases during the first event and has a positive value at an end of the first event, the second event to deactivate the first switch and activate the second switch wherein the switch control circuit maintains the current above zero during the second event, the third event to activate the first switch and deactivate the second switch, and the fourth event to deactivate the first switch and activate the second switch wherein the current decreases to a value below zero at an end of the fourth event and when the current reaches zero, a zero crossing time point is defined.

公开(公告)号：US09337795B2

公开(公告)日：2016-05-10

申请号：US14481201

申请日：2014-09-09

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Xin Zhao ,  Ted Burk ,  Ku He ,  John L. Melanson ,  Xiaofan Fei

IPC: H03F99/00 ,  H03G3/20 ,  H03G3/00 ,  H04R29/00

CPC classification number: H03G3/20 ,  H03G3/001 ,  H03G3/002 ,  H03G3/3005 ,  H03G3/3089

Abstract: A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error.

Abstract translation: 信号路径可以以多种增益模式之一操作，使得对于每个增益模式，与特定增益模式相关联的信号路径的数字增益和模拟信号增益的乘积近似等于固定路径增益。 在一个或多个校准阶段的每一个期间，校准系统可以测量第一路径部分的多个节点处的模拟信号，基于在多个节点处测量的模拟信号来计算与增益模式相关联的实际模拟增益，计算 固定路径增益与与增益模式相关联的实际模拟增益与与增益模式相关联的数字增益的数学乘积之间的误差，并且修改与增益模式相关联的数字增益和模拟增益中的至少一个 符合错误。

公开(公告)号：US20150303932A1

公开(公告)日：2015-10-22

申请号：US14255912

申请日：2014-04-17

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Xin Zhao ,  Xiaofan Fei

IPC: H03M1/00 ,  H03M1/36

CPC classification number: H03M1/002 ,  H03M1/0809 ,  H03M1/181 ,  H03M1/36

Abstract: A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

Abstract translation: 用于模数转换器（ADC）的比较器跟踪方案可以通过随时间变化多个比较器供电以将模拟输入信号转换为数字输出信号来实现动态窗口尺寸。 比较器跟踪方案可以例如在耦合到ADC中的多个比较器的控制器中实现。 例如，控制器可以确定ADC的窗口大小并确定ADC的窗口位置。 然后，控制器可以在以窗口位置为中心并且具有窗口大小的宽度的窗口内激活ADC的比较器。 控制器可以通过分析滤波器的输出来确定窗口大小。 当滤波器输出指示快速变化的模拟输入信号时，控制器可以动态增加ADC的窗口大小，这可能会增加多个比较器上电。

公开(公告)号：US20160080862A1

公开(公告)日：2016-03-17

申请号：US14483659

申请日：2014-09-11

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson

IPC: H04R3/00 ,  H03G3/20

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

公开(公告)号：US20150381130A1

公开(公告)日：2015-12-31

申请号：US14467969

申请日：2014-08-25

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Ku He ,  John L. Melanson

IPC: H03G3/20 ,  H04R3/02

CPC classification number: H04R3/02 ,  H03G3/001 ,  H03G3/002 ,  H03G3/3005 ,  H03G3/3026 ,  H03M1/70 ,  H04R2430/01

Abstract: In accordance with embodiments of the present disclosure, an apparatus for providing an output signal to an audio transducer may include a control circuit. The control circuit may be configured to predict, based on a magnitude of a signal indicative of the output signal, an occurrence of an event for changing a selectable digital gain and a selectable analog gain and an audio signal path, and responsive to predicting the occurrence of the event, change, at an approximate time in which a zero crossing of the signal indicative of the output signal occurs, the selectable digital gain and the selectable analog gain.

Abstract translation: 根据本公开的实施例，用于向音频换能器提供输出信号的装置可以包括控制电路。 控制电路可以被配置为基于指示输出信号的信号的大小来预测用于改变可选数字增益和可选择的模拟增益和音频信号路径的事件的发生，并且响应于预测发生 在发生指示输出信号的信号的零交叉的近似时间，可选择的数字增益和可选择的模拟增益之​​间改变事件。

公开(公告)号：US09998823B2

公开(公告)日：2018-06-12

申请号：US14507372

申请日：2014-10-06

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson ,  Anniruddha Satoskar

IPC: H04R3/00 ,  H03G3/20 ,  H03G3/00 ,  H04R3/04 ,  H03G3/30 ,  H03G9/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

公开(公告)号：US09596537B2

公开(公告)日：2017-03-14

申请号：US14483659

申请日：2014-09-11

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Tejasvi Das ,  John L. Melanson ,  Aniruddha Satoskar

IPC: H03G3/00 ,  H04R3/00 ,  H03G3/20 ,  H04R3/04 ,  H03G3/30 ,  H03F99/00

CPC classification number: H04R3/00 ,  H03G3/00 ,  H03G3/20 ,  H03G3/3005 ,  H03G3/3089 ,  H04R3/04 ,  H04R2430/00

Abstract: In accordance with embodiments of the present disclosure, a control circuit may be configured to, responsive to an indication to switch between gain modes of a signal path having an analog path portion and a digital signal path portion, switch a selectable analog gain of the analog path portion between a first analog gain and a second analog gain, switch a selectable digital gain of the digital signal path portion between a first digital gain and a second digital gain, wherein the product of the first analog gain and the first digital gain is approximately equal to the product of the second analog gain and the second digital gain, and control an analog response of the signal path to reduce the occurrence of audio artifacts present in the output signal as a result of the switch between gain modes of the signal path.A signal path may have an analog path portion and a digital signal path portion. The digital portion may have a selectable digitally-controlled gain and may be configured to convert a digital audio input signal into an analog input signal in conformity with the selectable digitally-controlled gain, the digital signal path portion comprising a modulator including a forward path and a feedback path. The forward path may include a loop filter for generating a filtered signal responsive to the digital audio input signal and a feedback signal, a quantizer responsive to the filtered signal for generating a quantized signal, and a first gain element configured to apply the selectable digitally-controlled gain to a signal within the forward path. The feedback path may be configured to generate the feedback signal responsive to the quantized signal, the feedback path including a second gain element having a gain inversely proportional to the selectable digitally-controlled gain.

Abstract translation: 信号路径可以具有模拟路径部分和数字信号路径部分。 数字部分可以具有可选择的数字控制的增益，并且可以被配置为将数字音频输入信号转换成符合可选数字控制的增益的模拟输入信号，数字信号路径部分包括调制器，包括前向路径和 反馈路径。 正向路径可以包括环路滤波器，用于响应于数字音频输入信号和反馈信号产生经滤波的信号，响应于经滤波的信号产生量化信号的量化器，以及第一增益元件，被配置为将可选择的数字 - 控制增益到正向路径内的信号。 反馈路径可以被配置为响应于量化信号产生反馈信号，反馈路径包括具有与可选数字控制增益成反比的增益的第二增益元件。

公开(公告)号：US09461537B1

公开(公告)日：2016-10-04

申请号：US14252244

申请日：2014-04-14

Applicant: Cirrus Logic, Inc.

Inventor： Xin Zhao ,  Ku He ,  John L. Melanson ,  Xiaofan Fei

IPC: G05F1/00 ,  H02M3/04 ,  G01R19/00

CPC classification number: H02M3/04 ,  G01R19/0084 ,  G01R19/0092 ,  G01R31/40 ,  H02M3/156 ,  H02M2001/0009

Abstract: A switch control circuit may be utilized for a sequence of switching events: a first event to activate a first switch and deactivate a second switch, wherein a current of an inductor coupled to the first switch and the second switch increases during the first event and has a positive value at an end of the first event; a second event to deactivate the first switch and activate the second switch, wherein the current of an inductor coupled to the first switch and the second switch decreases during the second event; and an impedance event during one of the first event and the second event such that during one of the first event and the second event, the impedance event causes an impedance of the one of the first switch and the second switch to decrease.

Abstract translation: 开关控制电路可以用于一系列切换事件：第一事件以激活第一开关并去激活第二开关，其中耦合到第一开关和第二开关的电感器的电流在第一事件期间增加并具有 在第一个事件结束时的正值; 第二事件，用于停用第一开关并激活第二开关，其中耦合到第一开关和第二开关的电感器的电流在第二事件期间减小; 以及在第一事件和第二事件之一期间的阻抗事件，使得在第一事件和第二事件之一期间，阻抗事件引起第一开关和第二开关中的一个的阻抗减小。