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公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US11288073B2
公开(公告)日：2022-03-29
申请号：US16854396
申请日：2020-04-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Ilya V. Perminov , Mark W. Johnson , Christopher B. Rich , Fabio Altomare , Trevor M. Lanting
IPC: G06F15/76 , G06F9/38 , G06N10/00 , G06F16/901 , H01L39/22
Abstract: A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
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公开(公告)号：US11422958B2
公开(公告)日：2022-08-23
申请号：US16872595
申请日：2020-05-12
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Andrew J. Berkley , Christopher B. Rich
Abstract: A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
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公开(公告)号：US10938346B2
公开(公告)日：2021-03-02
申请号：US15572731
申请日：2016-05-11
Applicant: D-Wave Systems Inc.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US11839164B2
公开(公告)日：2023-12-05
申请号：US16996595
申请日：2020-08-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E. G. Sterling , Christopher B. Rich
IPC: H10N60/12 , G11C11/44 , H03K3/38 , H03K17/92 , G11C8/00 , G06N10/40 , G11C8/10 , H10N60/80 , H10N69/00
CPC classification number: H10N60/12 , G06N10/40 , G11C8/00 , G11C8/10 , G11C11/44 , H03K3/38 , H03K17/92 , H10N60/805 , H10N69/00
Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
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Patent Agency Ranking
公开(公告)号：US20210013391A1
公开(公告)日：2021-01-14
申请号：US16098801
申请日：2017-05-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E.S. Johansson
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US20180145631A1
公开(公告)日：2018-05-24
申请号：US15572731
申请日：2016-05-11
Applicant: D-Wave Systems Inc.
Inventor： Andrew J. Berkley , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker , Paul I. Bunyk , Peter D. Spear , Christopher B. Rich
CPC classification number: H03B15/003 , G06N10/00 , H01L39/223 , H01P7/08 , H01P7/105 , H03B2201/02 , H03H7/01
Abstract: A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
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公开(公告)号：US20230004851A1
公开(公告)日：2023-01-05
申请号：US17782261
申请日：2020-12-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Christopher B. Rich
Abstract: A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.
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公开(公告)号：US11494683B2
公开(公告)日：2022-11-08
申请号：US16955526
申请日：2018-12-19
Applicant: D-Wave Systems Inc.
Inventor： Mohammad H. Amin , Paul I. Bunyk , Trevor M. Lanting , Chunqing Deng , Anatoly Smirnov , Kelly T. R. Boothby , Emile M. Hoskinson , Christopher B. Rich
Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).
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10.发明授权公开(公告)号：US11127893B2
公开(公告)日：2021-09-21
申请号：US16098801
申请日：2017-05-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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