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    Chip package
    6.
    发明授权
    Chip package 失效
    芯片封装

    公开(公告)号：US6046496A

    公开(公告)日：2000-04-04

    申请号：US964091

    申请日：1997-11-04

    Applicant: David Corisis ,  Walter Moden

    Inventor： David Corisis ,  Walter Moden

    IPC: H01L23/433 ,  H01L23/495 ,  H01L23/28

    CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2924/0002

    Abstract: The present invention relates to a heat management structure within a chip package that allows for heat rejection away from a chip but that avoids the prior art problems of thermal stresses caused by dissimilar thermal conductivities of a heat management structure and of creating a thermally unbalanced package due to disparate distribution of packaging plastic. In an embodiment of the present invention a package includes a chip, leads on the chip, a die attach, a downset, a packaging plastic, and an outer structure among others. The outer structure, downset, and die attach are together a substantially unitary article. Achieving a balanced package that substantially resists warpage and bowing during ordinary manufacture and ordinary use in the life of the package is accomplished by balancing packaging material width and the ability of the downset to resist warpage and bowing stresses. A substantial portion of the outer structure is exposed to the external part of the package in the surface which includes the packaging lower edge. Alternatively, the downset can include a part of the external boundary of the package such that exposure of the downset to the external portion of the package allows for additional heat rejection away from the chip in addition to the use of the outer structure.

    Abstract translation: 本发明涉及一种芯片封装内的热管理结构，其允许远离芯片的散热，但是避免了由热管理结构的不同热导率引起的热应力的现有技术问题，并且产生了热不平衡的封装 包装塑料分布不均匀。 在本发明的一个实施例中，封装包括芯片，芯片上的引线，管芯附接，压封，封装塑料和外部结构等。 外部结构，底部和管芯附着在一起是基本上一体的制品。 通过平衡包装材料宽度和降低翘曲和弯曲应力的能力，实现了在包装寿命期间普遍制造和普通使用中基本抵抗翘曲和弯曲的平衡包装。 外部结构的主要部分在包括封装下边缘的表面中暴露于封装的外部部分。 可替换地，下降装置可以包括包装的外部边界的一部分，使得除了外部结构的使用之外，向下的封装暴露于封装的外部部分还允许远离芯片的额外的散热。

    Heat sink for microchip application
    9.
    发明授权
    Heat sink for microchip application 有权
    散热片用于微芯片应用

    公开(公告)号：US06479326B1

    公开(公告)日：2002-11-12

    申请号：US09505391

    申请日：2000-02-16

    Applicant: David Corisis ,  Walter Moden

    Inventor： David Corisis ,  Walter Moden

    IPC: H01L2144

    CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to method of forming a chip package that includes a heat management structure that allows for heat rejection away from a chip but that avoids the prior art problems of thermal stresses caused by dissimilar thermal conductivities of a heat management structure and of creating a thermally unbalanced package due to disparate distribution of packaging plastic. In an embodiment of the present invention a package includes a chip, leads on the chip, a die attach, a downset, a packaging plastic, and an outer structure among others. The outer structure, downset, and die attach are together a substantially unitary article. Achieving a balanced package that substantially resists warpage and bowing during ordinary manufacture and ordinary use in the life of the package is accomplished by balancing packaging material width and the ability of the downset to resist warpage and bowing stresses. A substantial portion of the outer structure is exposed to the external part of the package in the surface which includes the packaging lower edge. Alternatively, the downset can include a part of the external boundary of the package such that exposure of the downset to the external portion of the package allows for additional heat rejection away from the chip in addition to the use of the outer structure.

    Abstract translation: 本发明涉及一种形成芯片封装的方法，该芯片封装包括热管理结构，该热管理结构允许散热从芯片脱离，但是避免了由热管理结构的不同热导率引起的热应力的现有技术问题， 由于包装塑料分布不均匀导致的热不平衡包装。 在本发明的一个实施例中，封装包括芯片，芯片上的引线，管芯附接，压封，封装塑料和外部结构等。 外部结构，底部和管芯附着在一起是基本上一体的制品。 通过平衡包装材料宽度和降低翘曲和弯曲应力的能力，实现了在包装寿命期间普遍制造和普通使用中基本抵抗翘曲和弯曲的平衡包装。 外部结构的主要部分在包括封装下边缘的表面中暴露于封装的外部部分。 可替换地，下降装置可以包括包装的外部边界的一部分，使得除了使用外部结构之外，向下的封装暴露于封装的外部部分还允许远离芯片的附加的热排除。

    Interconnect for packaging semiconductor dice and fabricating BGA packages
    10.
    发明授权
    Interconnect for packaging semiconductor dice and fabricating BGA packages 失效
    互连用于封装半导体芯片并制造BGA封装

    公开(公告)号：US06329222B1

    公开(公告)日：2001-12-11

    申请号：US09467643

    申请日：1999-12-20

    Applicant: David Corisis ,  Walter Moden

    Inventor： David Corisis ,  Walter Moden

    IPC: H01L2144

    CPC classification number: H01L23/49816 ,  H01L24/86 ,  H01L2224/05124 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

    Abstract: An interconnect for BGA packages, a BGA package fabricated using the interconnect, and a method for fabricating BGA packages using the interconnect, are provided. The interconnect includes multiple polymer substrates on which patterns of conductors are formed. Each substrate can be used to fabricate a BGA package. The conductors on the substrates include end portions having bonding vias formed therethrough in alignment with access openings in the substrates. During fabrication of the BGA packages, the bonding vias allow the conductors to be bonded to bond pads on semiconductor dice by forming metal bumps on the bonding vias and bond pads. The access openings in the substrates provide access to the bonding vias and bond pads for a bonding tool configured to form the metal bumps. In addition to the bonding vias, the conductors include ball bonding pads configured for attaching ball contacts, such as solder balls, to the conductors and substrates. The completed BGA package includes a substrate adhesively bonded to a semiconductor die; conductors with bonding vias on the substrate; metal bumps in the bonding vias bonding the conductors to bond pads on the die; and an area array of ball contacts attached to the conductors and substrate.

    Abstract translation: 提供用于BGA封装的互连，使用该互连制造的BGA封装以及使用该互连制造BGA封装的方法。 互连包括多个聚合物基底，其上形成有导体图案。 每个基板可用于制造BGA封装。 基板上的导体包括端部，其具有与基板中的进入开口对准的通孔形成的结合通孔。 在制造BGA封装期间，结合通孔允许通过在接合通孔和接合焊盘上形成金属凸块来将导体结合到半导体晶片上的接合焊盘。 衬底中的进入开口提供对用于形成金属凸块的接合工具的接合通路和接合焊盘的访问。 除了接合通孔之外，导体包括球形接合焊盘，其被配置用于将诸如焊球的球接触附接到导体和基板。 完成的BGA封装包括粘合到半导体管芯上的衬底; 在衬底上具有接合通孔的导体; 将导体粘接在芯片上的接合焊盘的接合通孔中的金属凸块; 以及附接到导体和基底的球形触点的面阵列。

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