公开(公告)号：US20130238859A1

公开(公告)日：2013-09-12

申请号：US13680243

申请日：2012-11-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH IN

Inventor： Jin Ho HAN

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/084 ,  G06F2212/6012 ,  Y02D10/13

Abstract: Disclosed are a cache with a scratch pad memory (SPM) structure and a processor including the same. The cache with a scratch pad memory structure includes: a block memory configured to include at least one block area in which instruction codes read from an external memory are stored; a tag memory configured to store an external memory address corresponding to indexes of the instruction codes stored in the block memory; and a tag controller configured to process a request from a fetch unit for the instruction codes, wherein a part of the block areas is set as a SPM area according to cache setting input from a cache setting unit. According to the present invention, it is possible to reduce the time to read instruction codes from the external memory and realize power saving by operating the cache as the scratch pad memory.

Abstract translation: 公开了具有便笺式存储器（SPM）结构的高速缓冲存储器和包括其的处理器。 具有暂存器存储器结构的高速缓存包括：块存储器，被配置为包括存储从外部存储器读取的指令代码的至少一个块区域; 标签存储器，被配置为存储对应于存储在块存储器中的指令代码的索引的外部存储器地址; 以及标签控制器，被配置为处理来自所述指令代码的取出单元的请求，其中，根据从高速缓存设置单元输入的高速缓存设置，将所述块区域的一部分设置为SPM区域。 根据本发明，可以减少从外部存储器读取指令代码的时间，并且通过操作高速缓存作为临时存储器来实现功率节省。