公开(公告)号：DE10334531B4

公开(公告)日：2009-07-09

申请号：DE10334531

申请日：2003-07-29

Applicant: ELPIDA MEMORY INC

Inventor： SHIBATA KAYOKO ,  NISHIO YOJI ,  FUNABA SEIJI

IPC: G06F13/00 ,  G06F13/16 ,  G06F12/00 ,  G11C5/06 ,  G11C11/4063 ,  H05K1/02

Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N-1)xZeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N-1)xZeffdimm/N 2 .

公开(公告)号：DE10235739A1

公开(公告)日：2003-03-27

申请号：DE10235739

申请日：2002-07-30

Applicant: ELPIDA MEMORY INC ,  HITACHI TOBU SEMICONDUCTOR LTD ,  HITACHI LTD

Inventor： NISHIO YOJI ,  FUNABA SEIJI ,  SHIBATA KAYOKO ,  SUGANO TOSHIO ,  IKEDA HIROAKI ,  IIZUKA TAKUO ,  SORIMACHI MASAYUKI

IPC: G11C11/407 ,  G06F12/00 ,  G06F12/06 ,  G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/409 ,  G06F1/04

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

公开(公告)号：DE10235740A1

公开(公告)日：2003-03-06

申请号：DE10235740

申请日：2002-07-30

Applicant: ELPIDA MEMORY INC ,  HITACHI TOBU SEMICONDUCTOR LTD ,  HITACHI LTD

Inventor： NISHIO YOJI ,  FUNABA SEIJI ,  SHIBATA KAYOKO ,  SUGANO TOSHIO ,  IKEDA HIROAKI ,  IIZUKA TAKUO ,  SORIMACHI MASAYUKI

IPC: G11C11/407 ,  G06F12/00 ,  G06F12/06 ,  G11C5/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  H03K5/14 ,  H03L7/081 ,  G11C7/22

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

公开(公告)号：DE10334531A1

公开(公告)日：2004-03-25

申请号：DE10334531

申请日：2003-07-29

Applicant: ELPIDA MEMORY INC

Inventor： SHIBATA KAYOKO ,  NISHIO YOJI ,  FUNABA SEIJI

IPC: G06F13/16 ,  G06F12/00 ,  G11C11/4063 ,  H05K1/02 ,  G06F13/00

Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N-1)xZeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N-1)xZeffdimm/N 2 .

公开(公告)号：DE10239626A1

公开(公告)日：2003-05-08

申请号：DE10239626

申请日：2002-08-23

Applicant: ELPIDA MEMORY INC

Inventor： ISA SATOSHI ,  FUNABA SEIJI

IPC: G06F3/00 ,  H01L29/80 ,  H03F1/56 ,  H03K19/0175 ,  H04B3/18 ,  H04L25/02

Abstract: A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.

公开(公告)号：DE10235739B4

公开(公告)日：2008-08-14

申请号：DE10235739

申请日：2002-07-30

Applicant: ELPIDA MEMORY INC

Inventor： NISHIO YOJI ,  FUNABA SEIJI ,  SHIBATA KAYOKO ,  SUGANO TOSHIO ,  IKEDA HIROAKI ,  IIZUKA TAKUO ,  SORIMACHI MASAYUKI

IPC: G06F1/04 ,  G11C11/407 ,  G06F12/00 ,  G06F12/06 ,  G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/409

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

公开(公告)号：DE102004062194A1

公开(公告)日：2005-08-11

申请号：DE102004062194

申请日：2004-12-23

Applicant: ELPIDA MEMORY INC

Inventor： NISHIO YOJI ,  FUNABA SEIJI

IPC: H01L23/14 ,  G06F1/18 ,  G06F13/00 ,  G11C5/02 ,  G11C7/00 ,  G11C11/407 ,  H01L21/68 ,  H01L23/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/065 ,  H01L25/07 ,  H01L27/108 ,  H05K1/14

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

公开(公告)号：DE102004049868A1

公开(公告)日：2005-06-30

申请号：DE102004049868

申请日：2004-10-13

Applicant: ELPIDA MEMORY INC

Inventor： FUNABA SEIJI ,  NISHIO YOJI

IPC: G11C11/408 ,  G11C5/06 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Each of stacked memory chips has an ID generator circuit for generating identification information in accordance with its manufacturing process. Since the memory chip manufacturing process implies process variations, the IDs generated by the respective ID generator circuits are different from one another even though the ID generator circuits are identical in design. A memory controller instructs an ID detector circuit to detect the IDs of the respective memory chips, and individually controls the respective memory chips based on the detected IDs.

公开(公告)号：DE10241451A1

公开(公告)日：2003-04-24

申请号：DE10241451

申请日：2002-09-06

Applicant: ELPIDA MEMORY INC

Inventor： FUNABA SEIJI ,  NISHIO YOJI

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/407

Abstract: In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.