公开(公告)号：DE10130752B4

公开(公告)日：2009-12-31

申请号：DE10130752

申请日：2001-06-26

Applicant: ELPIDA MEMORY INC

Inventor： YANAGISAWA TAKESHI

IPC: G11C8/08 ,  G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/408 ,  H03K3/03 ,  H03K3/70

Abstract: A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.