A METHOD AND SYSTEM FOR DEVICE VIRTUALIZATION BASED ON AN INTERRUPT REQUEST IN A DOS-BASED ENVIRONMENT
    1.
    发明申请
    A METHOD AND SYSTEM FOR DEVICE VIRTUALIZATION BASED ON AN INTERRUPT REQUEST IN A DOS-BASED ENVIRONMENT 审中-公开
    基于DOS的环境中的中断请求的设备虚拟化方法与系统

    公开(公告)号:WO1998011489A1

    公开(公告)日:1998-03-19

    申请号:PCT/US1997015813

    申请日:1997-09-08

    CPC classification number: G06F13/105 G06F9/45558 G06F2009/45579

    Abstract: A technique for providing device virtualization in an MS-DOS based operating environment (212), using an interrupt request (e.g., a non-maskable interrupt), is described. The technique includes executing an application on a processor within the MS-DOS based operating environment (212), and, when the application attempts to address the device to be emulated, causing a processor interrupt to occur. In response to the interrupt, the processor executes code representing the virtualization of a device. The code for servicing the interrupt and emulating the device are written in protected mode-code stored in the extended memory area (314), and made available by making appropriate entries into the interrup descriptor tables (318) for the protected-mode context established for the DOS extender (410). The entries made into IDT (318) for the protected-mode context established for the DOS extender are accomplished by intercepting communications between the DOS extender and the virtual control program interface (314).

    Abstract translation: 描述了使用中断请求(例如,不可屏蔽中断)在基于MS-DOS的操作环境(212)中提供设备虚拟化的技术。 该技术包括在基于MS-DOS的操作环境(212)内的处理器上执行应用程序,并且当应用程序尝试寻址待仿真的设备时,导致发生处理器中断。 响应于中断,处理器执行表示设备的虚拟化的代码。 用于维护中断和仿真设备的代码被写入存储在扩展存储器区域(314)中的保护模式代码中,并且通过为为中断描述符表(318)提供适当的条目而使得可用于为 DOS扩展器(410)。 通过拦截DOS扩展器和虚拟控制程序接口(314)之间的通信来实现为DOS扩展器建立的针对保护模式上下文的IDT(318)的条目。

    POWER EFFICIENT HEARING AID
    2.
    发明申请
    POWER EFFICIENT HEARING AID 审中-公开
    功率高效助听器

    公开(公告)号:WO1990010363A2

    公开(公告)日:1990-09-07

    申请号:PCT/US1990001178

    申请日:1990-03-02

    Abstract: A power efficient hearing aid uses a programmable biasing technique to set the quiescent operating points of amplifiers used by the hearing aid to avoid excessive power usage by the hearing aid. The hearing aid also includes power supply circuitry which develops +1.25 volts and -1.25 volts relative to ground from a single +1.25 volt source. The hearing aid also conserves power by selectively disabling low frequency signal processing channels in the presence of relatively large amplitude ambient noise.

    Abstract translation: 一种有效的功率听力假体使用可编程的偏置技术来调节由所述听力保护器使用的放大器的操作空闲点以避免所述助听器过度使用功率。 所述助听器还包括电源电路,该电源电路从+1.25伏的单一电源相对于地球产生+1.25伏和-1.25伏。 助听器还通过在存在相对高振幅的环境噪声的情况下选择性地关闭频率信号处理通道来节省功率。

    APPARATUS AND A METHOD FOR FITTING A HEARING AID
    3.
    发明申请
    APPARATUS AND A METHOD FOR FITTING A HEARING AID 审中-公开
    装置和配戴听力的方法

    公开(公告)号:WO1990009760A1

    公开(公告)日:1990-09-07

    申请号:PCT/US1990001175

    申请日:1990-03-02

    CPC classification number: H04R25/70 H04R25/505 H04R2430/03

    Abstract: A hearing aid fitting system includes a computer having a graphical display which controls apparatus that can program and evaluate an adjustable, multi-band hearing aid. The fitting procedure implemented on this system determines the combined frequency response characteristic of the hearing aid and a client's ear, determines maximum amplification factors which can be implemented in each channel without inducing feedback, and automatically adjusts the hearing aid so that the combination of the client's loss curve, the determined combined frequency response characteristic, and the adjusted hearing aid match a target curve. The target curve and the loss curve may be graphically specified and adjusted using the computer.

    Abstract translation: 助听器配件系统包括具有图形显示器的计算机,该图形显示器控制可编程和评估可调节的多频段助听器的装置。 在该系统上实施的拟合程序确定助听器和客户耳朵的组合频率响应特性,确定可以在每个通道中实现的最大放大因子而不引起反馈,并自动调整助听器,使得客户端 损失曲线,确定的组合频率响应特性和调整后的助听器匹配目标曲线。 目标曲线和损失曲线可以使用计算机图形化指定和调整。

    DECIMATION FILTER AS FOR A SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER
    5.
    发明申请
    DECIMATION FILTER AS FOR A SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER 审中-公开
    用于SIGMA-DELTA模拟数字转换器的十进制滤波器

    公开(公告)号:WO1990013942A1

    公开(公告)日:1990-11-15

    申请号:PCT/US1990002565

    申请日:1990-05-08

    CPC classification number: H03H17/0685 H03H17/0227 H03H17/0614

    Abstract: A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 49 KHz and a sample resolution of 16 bits from an input signals having a sampling rate of 3.072 MHz and a sample resolution of one bit. The filter uses a single read-only memory (820) to hold the 2048 coefficient values. The coefficient values are distributed to eight four-way multiplexed accumulators by a circuitry which includes a signal multiplexer (822) and a barrel shifter (824). The accumulators use unsigned arithmetic to calculate the output sample values. A value CO, representing a normalizing offset (812) and gain applied to each of the coefficient values, is selected such that 2048 times CO is a value which overflows the accumulator, leaving a value of zero in the accumulator.

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