公开(公告)号：US20130191797A1

公开(公告)日：2013-07-25

申请号：US13674281

申请日：2012-11-12

Applicant: Electronics and Telecommunications Research In

Inventor： Soon Il YEO ,  Young Ho KIM

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66 ,  G06F2217/82

Abstract: Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP.

Abstract translation: 公开了一种设计半导体芯片的方法和设备。 所公开的方法包括以下步骤：存储多个EMS（电磁敏感性）半导体IP（知识产权）和多个EMI（电磁干扰）半导体IP; 在输入引脚的情况下从多个EMS屏蔽半导体IP中选择适当的半导体IP，并且在输出引脚的情况下从多个EMI屏蔽半导体IP中选择合适的半导体IP; 以及通过配置所选择的半导体IP来设计半导体芯片。