公开(公告)号：WO1980000375A1

公开(公告)日：1980-03-06

申请号：PCT/US1979000556

申请日：1979-07-30

Applicant: FLUKE TRENDAR CORP

Inventor： FLUKE TRENDAR CORP ,  SAPER B ,  LAM T

IPC: G01R31/26

CPC classification number: G01R31/318385 ,  G01R31/3193 ,  G06F11/277 ,  G06F2201/83

Abstract: An apparatus and method for identifying faults in a digital logic circuit system (26) combines the output of a feedback signature generator (14) and synchronous transition counter (16) to provide a unique signature which is sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals via signal lines (32) of the circuit system (26) which are produced in response to a preselected input signal pattern of a test signal generator (24) is processed synchronously under control of a sequence controller (38) through a feedback signature generator (14), such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network (16). A preselected portion of the output of the bit transition counting network (16) is combined via a signal line (82) with a preselected portion of the bits of the feedback signature generator (14) to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system (26) under test. The fault detecting capability approaches one hundred percent with an embedded indication of the input test pattern duration as verification.

公开(公告)号：ZA7904049B

公开(公告)日：1980-07-30

申请号：ZA7904049

申请日：1979-08-06

Applicant: FLUKE TRENDAR

Inventor： LAM TIM YEE ,  TIM YEE LAM ,  SAPER B

IPC: G01R31/3193 ,  G06F11/277 ,  G06F ,  G01R

CPC classification number: G01R31/318385 ,  G01R31/3193 ,  G06F11/277 ,  G06F2201/83

公开(公告)号：ZA794049B

公开(公告)日：1980-07-30

申请号：ZA794049

申请日：1979-08-06

Applicant: FLUKE TRENDAR

Inventor： LAM TIM YEE ,  TIM YEE LAM ,  SAPER B

IPC: G01R31/3193 ,  G06F11/277 ,  G06F ,  G01R

Abstract: An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network. A preselected portion of the output of the bit transition counting network is combined with a preselected portion of the bits of the shift register network to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system under test. The fault detecting capability approaches 100 percent with an imbedded indication of the input test pattern duration as verification.