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    Device having reduced bias temperature instability (bti)
    4.
    发明公开
    Device having reduced bias temperature instability (bti) 有权
    具有降低的偏置温度不稳定性（bti）的器件

    公开(公告)号：EP2696366A3

    公开(公告)日：2014-11-12

    申请号：EP13179428.1

    申请日：2013-08-06

    Applicant: General Electric Company

    Inventor： Michael, Joseph Darryl ,  Arthur, Stephen Daley ,  Johnson, Tammy Lynn ,  Lilienfeld, David Alan

    IPC: H01L21/04 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/0485 ,  H01L29/66068 ,  H01L29/7827

    Abstract: A semiconductor device (100) is disclosed along with methods (10) for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode (124) formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.

    Abstract translation: 公开了半导体器件（100）以及用于制造这种器件的方法（10）。 在某些实施例中，半导体器件包括使用金属形成的源电极（124），所述金属在操作期间在半导体器件的阈值电压中限制诸如由于偏置温度不稳定性的偏移。 在某些实施例中，半导体器件可以基于碳化硅。

    A silicon-carbide mosfet cell structure and method for forming same
    7.
    发明公开
    A silicon-carbide mosfet cell structure and method for forming same 审中-公开
    碳化硅MOSFET单元结构及其制造方法

    公开(公告)号：EP2551912A3

    公开(公告)日：2014-11-05

    申请号：EP12177404.6

    申请日：2012-07-20

    Applicant: General Electric Company

    Inventor： Arthur, Stephen Daley ,  Matocha, Kevin ,  Sandvik, Peter ,  Stum, Zachary ,  Losee, Peter ,  McMahon, James

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L27/088 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

    Abstract: In one embodiment, the invention comprises a silicon-carbide MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body region (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and body regions (252). Gate oxide and a gate contact overlie a leg of a well of a first cell and a leg of a well of a second adjacent cell, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

    Method and system for transient voltage suppressors
    8.
    发明公开
    Method and system for transient voltage suppressors 审中-公开
    Verfahren undÜberspannungsschutzanordnung

    公开(公告)号：EP2587543A3

    公开(公告)日：2014-04-09

    申请号：EP12189922.3

    申请日：2012-10-25

    Applicant: General Electric Company

    Inventor： Kashyap, Avinash Srikrishnan ,  Shaddock, David Mulford ,  Andarawis, Emad ,  Sandvik, Peter Micah ,  Arthur, Stephen Daley

    IPC: H01L29/861 ,  H01L29/06 ,  H01L29/16

    CPC classification number: H01L21/56 ,  H01L23/3185 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/861 ,  H01L29/8618 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly (218) and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die (302) in a mesa structure that includes a first layer (306) of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer (308) of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer (312) of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

    Abstract translation: 提供了形成碳化硅瞬态电压抑制器（TVS）组件（218）和用于瞬态电压抑制器（TVS）组件的系统的方法。 TVS组件包括台面结构中的半导体管芯（302），其包括具有第一极性的导电率的第一宽带隙半导体的第一层（306），第一或第二宽度的第二层（308） 带隙半导体具有与第一层电接触的第二极性的导电性，其中第二极性不同于第一极性。 TVS组件还包括具有与第二层电接触的第一极性的导电性的第一，第二或第三宽带隙半导体的第三层（312）。 具有第二极性的导电性的层相对于具有第一极性的导电性的层被轻掺杂。

    Device having reduced bias temperature instability (bti)
    9.
    发明公开
    Device having reduced bias temperature instability (bti) 有权
    Vorrichtung mit verminderterVorspannungstemperaturinstabilität（bti）

    公开(公告)号：EP2696366A2

    公开(公告)日：2014-02-12

    申请号：EP13179428.1

    申请日：2013-08-06

    Applicant: General Electric Company

    Inventor： Michael, Joseph Darryl ,  Arthur, Stephen Daley ,  Johnson, Tammy Lynn ,  Lilienfeld, David Alan

    IPC: H01L21/04 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/0485 ,  H01L29/66068 ,  H01L29/7827

    Abstract: A semiconductor device (100) is disclosed along with methods (10) for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode (124) formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.

    Abstract translation: 公开了半导体器件（100）以及用于制造这种器件的方法（10）。 在某些实施例中，半导体器件包括使用在操作期间半导体器件的阈值电压限制诸如由于偏置温度不稳定性引起的偏移的金属形成的源极（124）。 在某些实施例中，半导体器件可以基于碳化硅。

    Hermetically sealed package for a silicon carbide semiconductor device
    10.
    发明公开
    Hermetically sealed package for a silicon carbide semiconductor device 审中-公开
    气密密封的外壳由碳化硅制成的半导体器件

    公开(公告)号：EP2693469A2

    公开(公告)日：2014-02-05

    申请号：EP13178277.3

    申请日：2013-07-26

    Applicant: General Electric Company

    Inventor： Michael, Joseph Darryl ,  Arthur, Stephen Daley

    IPC: H01L23/04 ,  H01L21/50

    CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L29/1608 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system includes a silicon carbide (SiC) semiconductor device (100) and a hermetically sealed packaging (130) enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere (132) near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.

    Abstract translation: 一种系统，包括碳化硅（SiC）的半导体器件（100）和一个密封的包装（130）包围的SiC半导体器件。 气密密封的包装是被配置为保持特定气氛（132）的SiC半导体器件的附近。 此外，特定气氛限制了在SiC半导体器件的阈值电压到小于1V操作期间的移动。

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