公开(公告)号：US09299665B2

公开(公告)日：2016-03-29

申请号：US14519235

申请日：2014-10-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Paul S. Andry ,  Cyril Cabral, Jr. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC: H01L23/556 ,  H01L23/00 ,  H01L21/304 ,  H01L21/48

CPC classification number: H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

Abstract: A structure fabrication method. An integrated circuit that includes N chip electric pads is bonded to a top side of an interposing shield that includes N electric conductors. N is at least 2. The interposing shield includes a shield material that includes a first semiconductor material. A bottom side of the interposing shield is polished, which exposes the N electric conductors to a surrounding ambient. The bonding includes bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact and direct physical contact with corresponding electrical pads of the N electric conductors. The shield material covers the N electric conductors in a manner that the N electric conductors are not exposed to the surrounding ambient. The polishing removes a sufficient amount of the shield material to expose the N electric conductors to the surrounding ambient.

Abstract translation: 一种结构制造方法。 包括N个芯片电焊盘的集成电路被结合到包括N个电导体的插入屏蔽的顶侧。 N为至少2.插入屏蔽包括包括第一半导体材料的屏蔽材料。 中间屏蔽的底面被抛光，将N根电导体暴露在周围环境中。 接合包括将集成电路接合到中间屏蔽的顶侧，使得N个芯片电极焊盘与N个电导体的相应电焊盘电接触并直接物理接触。 屏蔽材料以N个电导体不暴露于周围环境的方式覆盖N个电导体。 抛光去除了足够量的屏蔽材料，以将N个电导体暴露于周围环境。

公开(公告)号：US09299847B2

公开(公告)日：2016-03-29

申请号：US14741169

申请日：2015-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qinghuang Lin ,  Minhua Lu ,  Robert L. Wisnieff

IPC: H01L23/48 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L23/532 ,  H01L21/283 ,  H01L51/00

CPC classification number: H01L29/78633 ,  H01L21/283 ,  H01L23/532 ,  H01L23/5329 ,  H01L27/1292 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/7869 ,  H01L51/0004 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

公开(公告)号：US09236250B2

公开(公告)日：2016-01-12

申请号：US13924064

申请日：2013-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Robert L. Wisnieff

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L21/02447 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/1606 ,  H01L29/267

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.