公开(公告)号：US10062692B1

公开(公告)日：2018-08-28

申请号：US15443381

申请日：2017-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shishir K. Ray ,  Bharat V. Krishnan ,  Jinping Liu ,  Meera S. Mohan ,  Joseph K. Kassim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306 ,  H01L29/167 ,  H01L21/285 ,  H01L29/45

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

公开(公告)号：US10134876B2

公开(公告)日：2018-11-20

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. Krishnan ,  Timothy J. McArdle ,  Rinus Tek Po Lee ,  Shishir K. Ray ,  Akshey Sehgal

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US09679810B1

公开(公告)日：2017-06-13

申请号：US15041203

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20180286982A1

公开(公告)日：2018-10-04

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. KRISHNAN ,  Timothy J. MCARDLE ,  Rinus Tek Po LEE ,  Shishir K. Ray ,  Akshey SEHGAL

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.