公开(公告)号：US20160043190A1

公开(公告)日：2016-02-11

申请号：US14454778

申请日：2014-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth BANGHART ,  Mitsuhiro TOGO ,  Shesh Mani PANDEY

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

Abstract translation: 提供半导体结构和制造方法，其中一个或两个扩展的源到沟道接口或延伸的漏极到沟道的接口。 制造方法包括例如使半导体材料凹陷以形成与正在制造的半导体结构的沟道区相邻的空腔，凹陷在空腔内形成第一空腔表面和第二空腔表面; 以及通过所述第一空腔表面将一种或多种掺杂剂注入所述半导体材料中以限定所述半导体材料内的注入区域，并且形成扩展的沟道界面，所述扩展沟道界面部分地包括所述半导体内的所述注入区域的界面 材料到半导体结构的沟道区域。 在一个实施例中，具有扩展通道接口的半导体结构是FinFET。

公开(公告)号：US20160118500A1

公开(公告)日：2016-04-28

申请号：US14523548

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

公开(公告)号：US20170222054A1

公开(公告)日：2017-08-03

申请号：US15491465

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth BANGHART ,  Mitsuhiro TOGO ,  Shesh Mani PANDEY

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

公开(公告)号：US20170084718A1

公开(公告)日：2017-03-23

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.