公开(公告)号：US20160163644A1

公开(公告)日：2016-06-09

申请号：US14561359

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag WOO ,  Ryan Ryoung-han KIM

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract translation: 公开了一种形成具有均匀的规则形状的栅极触点的半导体器件的方法以及所得到的器件。 实施例包括在基板上形成彼此相邻的第一和第二栅电极; 在所述第一和第二栅电极之间的所述衬底上形成至少一个沟槽硅化物（TS）; 在第一栅电极上形成栅极接触，栅接触具有规则形状; 在所述第一和第二栅电极之间的沟槽硅化物上形成源极/漏极接触，其中所述源极/漏极接触部的上部与所述栅极接触件的上部重叠。

公开(公告)号：US20170141110A1

公开(公告)日：2017-05-18

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US20160293496A1

公开(公告)日：2016-10-06

申请号：US15168336

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han KIM

IPC: H01L21/8238 ,  H01L27/118 ,  H01L27/092 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L21/823871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/6681 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

公开(公告)号：US20160365288A1

公开(公告)日：2016-12-15

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L21/8238 ,  H01L23/528 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20160293495A1

公开(公告)日：2016-10-06

申请号：US15167347

申请日：2016-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han KIM

IPC: H01L21/8238 ,  H01L27/118 ,  H01L27/092 ,  H01L23/535 ,  H01L27/02

CPC classification number: H01L21/823871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/6681 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

Abstract translation: 提供了利用TS栅极交叉耦合结构形成逻辑单元的方法以及所得到的器件。 实施例包括在基板上形成有源翅片和虚拟翅片，虚拟翅片彼此相邻并且在活动翅片之间; 在活动和虚拟翅片之间和之后形成STI区域; 在主动和虚拟翅片上平行地形成栅极结构; 通过切割所述虚拟翅片之间的栅极结构来形成栅极切割区域; 在所述栅极结构之间形成TS层，所述TS层穿过所述栅极截止区域; 以及在所述栅极切割区域的第一侧上形成连接栅极结构和所述TS层的接触，并且在所述栅极切割区域的第二侧上形成连接栅极结构和所述TS层的接触部，所述TS层和所述接触部分交叉耦合 门结构。

公开(公告)号：US20160111341A1

公开(公告)日：2016-04-21

申请号：US14515140

申请日：2014-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-han KIM

IPC: H01L21/8238 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/6681 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.