公开(公告)号：US10991689B2

公开(公告)日：2021-04-27

申请号：US16376234

申请日：2019-04-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abu Naser M. Zainuddin ,  Christopher D. Sheraw ,  Sangameshwar Rao Saudari ,  Wei Ma ,  Kai Zhao ,  Bala S Haran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.

公开(公告)号：US10991796B2

公开(公告)日：2021-04-27

申请号：US16231671

申请日：2018-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Lin Hu ,  Veeraraghavan S. Basker ,  Brian J. Greene ,  Kai Zhao ,  Daniel Jaeger ,  Keith Tabakman ,  Christopher Nassar

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.