公开(公告)号：US10509433B2

公开(公告)日：2019-12-17

申请号：US15762894

申请日：2016-09-23

Applicant: Gemalto SA

Inventor： Philippe Loubet Moundi ,  Jean-Roch Coulon ,  Jorge Ernesto Perez Chamorro

IPC: G06F1/06 ,  G06F7/58 ,  H03K3/84 ,  G06F1/08 ,  G06F21/72

Abstract: The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.