公开(公告)号：US09166569B2

公开(公告)日：2015-10-20

申请号：US14166637

申请日：2014-01-28

Applicant: Generalplus Technology Inc.

Inventor： Shih-Ming Luo ,  Min Lu

IPC: H03K3/0231 ,  H03K4/501 ,  H03K3/03

CPC classification number: H03K3/0231 ,  H03K3/03 ,  H03K4/501

Abstract: A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.

Abstract translation: 在本发明中提供了张弛振荡器。 张弛振荡器包括R-S锁存器，第一延迟电路和第二延迟电路。 第一延迟电路的输入端耦合到R-S锁存器的Q输出端，第一延迟电路的输出端耦合到R-S锁存器的复位端。 第二延迟电路的输入端耦合到R-S锁存器的反相Q输出端，第二延迟电路的输出端耦合到R-S锁存器的设定端。 当第一延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第一延迟电路的输出端输出第二逻辑脉冲。 当第二延迟电路的输入端输入第一逻辑电压时，在延迟时间之后，第二延迟电路的输出端输出第二逻辑脉冲。