公开(公告)号：US20230290880A1

公开(公告)日：2023-09-14

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam DUTTA ,  Vvss Satyasuresh CHOPPALLI ,  Rajendran KRISHNASAMY

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0611

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US20230420561A1

公开(公告)日：2023-12-28

申请号：US17849279

申请日：2022-06-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam DUTTA ,  Partha S. GUPTA

IPC: H01L29/78 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/7841 ,  H01L27/105 ,  H01L27/1203 ,  H01L29/24

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to memory devices and methods of manufacture. The structure includes: a gate structure having a gate dielectric material and a gate body; a body region under the gate dielectric material; a first doped region laterally adjacent to a first side of the body region; a second doped region laterally adjacent to the first doped region; and a shallow trench isolation structure laterally adjacent to a second side of the body region.

公开(公告)号：US20230352536A1

公开(公告)日：2023-11-02

申请号：US17734135

申请日：2022-05-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh CHOPPALLI ,  Anupam DUTTA ,  Aaron Lee VALLETT

IPC: H01L29/10 ,  H01L21/74

CPC classification number: H01L29/1087 ,  H01L21/743

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

公开(公告)号：US20220359572A1

公开(公告)日：2022-11-10

申请号：US17872812

申请日：2022-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam DUTTA

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

公开(公告)号：US20240145585A1

公开(公告)日：2024-05-02

申请号：US17978633

申请日：2022-11-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam DUTTA ,  Rajendran KRISHNASAMY ,  Vvss Satyasuresh CHOPPALLI ,  Vibhor JAIN ,  Robert J. Gauthier, JR.

IPC: H01L29/737

CPC classification number: H01L29/7375

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a heterojunction bipolar transistor comprising a collector region, a base region and an emitter region; and at least one non-single-crystal semiconductor region in the collector region of the heterojunction bipolar transistor.