公开(公告)号：EP4418268A1

公开(公告)日：2024-08-21

申请号：EP23191931.7

申请日：2023-08-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Pasupula, Suresh ,  Dwivedi, Devesh

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2~1/2∗VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

公开(公告)号：EP4492685A1

公开(公告)日：2025-01-15

申请号：EP24151286.2

申请日：2024-01-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar

IPC: H03K3/356

Abstract: Disclosed structures include a single-stage (100) and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter (100) and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (IN1, IN1B) (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (OUT1i, OUT1Bi) (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse (OUT1, OUT1B) that transitions between ground and V2) can be output.

公开(公告)号：EP4462679A1

公开(公告)日：2024-11-13

申请号：EP23208142.2

申请日：2023-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Ara, Venu Gopal Reddy ,  Dwivedi, Devesh

IPC: H03K5/133 ,  H03K19/0185 ,  H03K19/20

Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure (100) of the disclosure includes a first pair of complementary transistors (112) connected in series between a first voltage node (V1) and a second voltage node (V2). Each transistor of the first pair includes a gate coupled to a first input node (N1). A second pair of complementary transistors (114) is connected in series between the first voltage node (V1) and the second voltage node (V2) in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node (N2). An output line (Vout) is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

公开(公告)号：EP4358086A1

公开(公告)日：2024-04-24

申请号：EP23192048.9

申请日：2023-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chinthu, Siva Kumar ,  Pasupula, Suresh ,  Dwivedi, Devesh ,  Chiang, Chunsung

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/004220130101 ,  G11C2013/004520130101 ,  G11C2013/005420130101 ,  G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/06320130101 ,  G11C11/1673

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.