公开(公告)号：EP4357770A1

公开(公告)日：2024-04-24

申请号：EP23192055.4

申请日：2023-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pawlak, Bartlomiej J. ,  Levy, Mark D. ,  Adusumilli, Siva P. ,  Hazbun, Ramsey M.

IPC: G01N27/414 ,  B01L3/00 ,  G01N33/00 ,  G01N27/64

CPC classification number: G01N27/414 ,  G01N27/64 ,  G01N33/48707

Abstract: A structure (100) includes a cavity (140) in a semiconductor substrate (108); a field effect transistor (112) positioned over the cavity (140); an opening (130) in the semiconductor substrate (108) extending to the cavity (140); and a layer of insulating material (132) filling the opening (130) and forming an insulating material window (132) to the cavity (140).

公开(公告)号：EP4386830A1

公开(公告)日：2024-06-19

申请号：EP23201726.9

申请日：2023-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pandey, Shesh Mani ,  Levy, Mark D. ,  Tan, Chung Foong

IPC: H01L23/34 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/345

Abstract: A fuse structure includes a fuse body including a polysilicon, and a metal heater over the fuse body. The fuse structure also includes a heating spreading structure thermally coupled to the metal heater and extending horizontally adjacent to at least one side of the fuse body. The metal heater can be a portion of a metal wire or a resistor including a resistive metal. The heat spreading structure may include a plurality of metal contacts.

公开(公告)号：EP4386859A1

公开(公告)日：2024-06-19

申请号：EP23204762.1

申请日：2023-10-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sharma, Santosh ,  Levy, Mark D.

IPC: H01L29/778 ,  H01L29/10 ,  H01L27/06 ,  H01L29/417 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/1066 ,  H01L29/41766 ,  H01L27/0605 ,  H01L27/085 ,  H01L21/8252

Abstract: A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer (103) with a thick portion (103T) positioned laterally between thin portions (103t) and a gate. The gate includes a semiconductor layer (132) (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion (132T) positioned laterally between thin portions (132t). The gate also includes a gate conductor layer (133) on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.