公开(公告)号：US20180276068A1

公开(公告)日：2018-09-27

申请号：US15468619

申请日：2017-03-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: H03M13/2906 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

公开(公告)号：US11153008B1

公开(公告)日：2021-10-19

申请号：US16946078

申请日：2020-06-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Robert R. Imark ,  Brian S. Birk

IPC: H04B10/00 ,  H04B10/077

Abstract: Examples described herein relate to method for measuring a disconnect response time. The method includes discontinuing, in response to a determining that a disconnect response metric test is to be initiated, transmission of a test optical signal by a test device to a DUT coupled to the test device, wherein the DUT is to discontinue transmission of a response optical signal to the test device upon detection of a loss of the test optical signal. Further, a loss of the response optical signal by may be detected by the test device. Furthermore, a disconnect response metric of the DUT may be determined by the test device based on a time of discontinuation of the transmission of the test optical signal and a time of detection of the loss of the response optical signal.

公开(公告)号：US10312943B2

公开(公告)日：2019-06-04

申请号：US15468619

申请日：2017-03-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

IPC: H03M13/00 ,  H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

公开(公告)号：US10474389B2

公开(公告)日：2019-11-12

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

公开(公告)号：US20180011660A1

公开(公告)日：2018-01-11

申请号：US15201981

申请日：2016-07-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Brian S. Birk ,  Joseph F. Orth ,  Harvey Ray ,  Craig Warner

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673 ,  G06F3/0679

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.