公开(公告)号：WO2016068907A1

公开(公告)日：2016-05-06

申请号：PCT/US2014/062886

申请日：2014-10-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： LESARTRE, Gregg B. ,  SHERLOCK, Derek A.

IPC: G06F12/00

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0246 ,  G06F17/30997

Abstract: An example system for committing metadata to a non-volatile storage device may include a controller that includes determines a count of metadata that has been altered after being committed to the non-volatile storage device. Based on the count being above a first threshold, the controller may prevent alterations to the metadata. Based on the count being above a second threshold, the controller may commit the altered metadata to the non-volatile metadata.

Abstract translation: 将元数据提交给非易失性存储设备的示例系统可以包括控制器，其包括确定在提交到非易失性存储设备之后已被改变的元数据的计数。 基于计数高于第一阈值，控制器可以防止对元数据的改变。 基于计数高于第二阈值，控制器可以将改变的元数据提交给非易失性元数据。

公开(公告)号：WO2016122602A1

公开(公告)日：2016-08-04

申请号：PCT/US2015/013795

申请日：2015-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： LESARTRE, Gregg B. ,  SHERLOCK, Derek A. ,  TAVALLAEI, Siamak

IPC: G06F12/06

CPC classification number: G06F11/1076 ,  G06F2211/1088

Abstract: A computing system including a processor and a memory controller coupled to a plurality of remote memory modules, which implement a redundancy protocol and support a direct access request. The memory controller is to receive a block access request from the processor and, based on the redundancy model, reformat the block access request into a direct access request and transmit the request to the plurality of remote memory modules. The memory controller reformats the block access request to maintain data consistency in accordance with the redundancy protocol.

Abstract translation: 一种计算系统，包括耦合到多个远程存储器模块的处理器和存储器控制器，其实现冗余协议并支持直接访问请求。 存储器控制器将从处理器接收块访问请求，并且基于冗余模型将块访问请求重新格式化为直接访问请求，并将请求发送到多个远程存储器模块。 存储器控制器重新格式化块访问请求，以根据冗余协议维护数据一致性。

公开(公告)号：WO2016064403A1

公开(公告)日：2016-04-28

申请号：PCT/US2014/061965

申请日：2014-10-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： SHERLOCK, Derek A.

IPC: G06F12/00 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F12/1027 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/145 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.

Abstract translation: 系统包括中央处理单元（CPU），用于处理关于由CPU生成的虚拟地址的数据。 第一存储器管理单元（MMU）将虚拟地址相对于由CPU处理的数据转换为存储器的物理地址。 监控MMU将第一MMU的物理地址转换为存储地址，以存储和检索存储器中的数据。 监控MMU通过由第一MMU生成的存储地址来控制对存储器的访问。